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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Deepika Bhavnani6bd46662019-08-15 00:56:46 +03002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <string.h>
9
Dan Handley2bd4ef22014-04-09 13:14:54 +010010#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <common/bl_common.h>
13#include <common/debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010014#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/el3_runtime/context_mgmt.h>
16#include <lib/utils.h>
17#include <plat/common/platform.h>
18
Dan Handley714a0d22014-04-09 13:13:04 +010019#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
Achin Gupta607084e2014-02-09 18:24:19 +000021/*
Jeenu Viswambharan7f366602014-02-20 17:11:00 +000022 * SPD power management operations, expected to be supplied by the registered
23 * SPD on successful SP initialization
Achin Gupta607084e2014-02-09 18:24:19 +000024 */
Dan Handleye2712bc2014-04-10 15:37:22 +010025const spd_pm_ops_t *psci_spd_pm;
Achin Gupta607084e2014-02-09 18:24:19 +000026
Soby Mathew981487a2015-07-13 14:10:57 +010027/*
28 * PSCI requested local power state map. This array is used to store the local
29 * power states requested by a CPU for power levels from level 1 to
30 * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power
31 * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a
32 * CPU are the same.
33 *
34 * During state coordination, the platform is passed an array containing the
35 * local states requested for a particular non cpu power domain by each cpu
36 * within the domain.
37 *
38 * TODO: Dense packing of the requested states will cause cache thrashing
39 * when multiple power domains write to it. If we allocate the requested
40 * states at each power level in a cache-line aligned per-domain memory,
41 * the cache thrashing can be avoided.
42 */
43static plat_local_state_t
44 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
45
Pankaj Gupta02c35682019-10-15 15:44:45 +053046unsigned int psci_plat_core_count;
Soby Mathew981487a2015-07-13 14:10:57 +010047
Achin Gupta4f6ad662013-10-25 09:08:21 +010048/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010049 * Arrays that hold the platform's power domain tree information for state
50 * management of power domains.
51 * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain
52 * which is an ancestor of a CPU power domain.
53 * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain
Achin Gupta4f6ad662013-10-25 09:08:21 +010054 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010055non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]
Soby Mathew2ae20432015-01-08 18:02:44 +000056#if USE_COHERENT_MEM
Soren Brinkmann46dd1702016-01-14 10:11:05 -080057__section("tzfw_coherent_mem")
Soby Mathew2ae20432015-01-08 18:02:44 +000058#endif
59;
Achin Gupta4f6ad662013-10-25 09:08:21 +010060
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +000061/* Lock for PSCI state coordination */
62DEFINE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
Andrew Thoelkee466c9f2015-09-10 11:39:36 +010063
Soby Mathew981487a2015-07-13 14:10:57 +010064cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
65
Achin Gupta4f6ad662013-10-25 09:08:21 +010066/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010067 * Pointer to functions exported by the platform to complete power mgmt. ops
68 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010069const plat_psci_ops_t *psci_plat_pm_ops;
Achin Gupta4f6ad662013-10-25 09:08:21 +010070
Soby Mathew981487a2015-07-13 14:10:57 +010071/******************************************************************************
72 * Check that the maximum power level supported by the platform makes sense
73 *****************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010074CASSERT((PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL) &&
75 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),
76 assert_platform_max_pwrlvl_check);
Soby Mathew2b7de2b2015-02-12 14:45:02 +000077
Soby Mathew981487a2015-07-13 14:10:57 +010078/*
79 * The plat_local_state used by the platform is one of these types: RUN,
80 * RETENTION and OFF. The platform can define further sub-states for each type
81 * apart from RUN. This categorization is done to verify the sanity of the
82 * psci_power_state passed by the platform and to print debug information. The
83 * categorization is done on the basis of the following conditions:
84 *
85 * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN.
86 *
87 * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is
88 * STATE_TYPE_RETN.
89 *
90 * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is
91 * STATE_TYPE_OFF.
92 */
93typedef enum plat_local_state_type {
94 STATE_TYPE_RUN = 0,
95 STATE_TYPE_RETN,
96 STATE_TYPE_OFF
97} plat_local_state_type_t;
98
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010099/* Function used to categorize plat_local_state. */
100static plat_local_state_type_t find_local_state_type(plat_local_state_t state)
101{
102 if (state != 0U) {
103 if (state > PLAT_MAX_RET_STATE) {
104 return STATE_TYPE_OFF;
105 } else {
106 return STATE_TYPE_RETN;
107 }
108 } else {
109 return STATE_TYPE_RUN;
110 }
111}
Soby Mathew981487a2015-07-13 14:10:57 +0100112
113/******************************************************************************
114 * Check that the maximum retention level supported by the platform is less
115 * than the maximum off level.
116 *****************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100117CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE,
Soby Mathew981487a2015-07-13 14:10:57 +0100118 assert_platform_max_off_and_retn_state_check);
119
120/******************************************************************************
121 * This function ensures that the power state parameter in a CPU_SUSPEND request
122 * is valid. If so, it returns the requested states for each power level.
123 *****************************************************************************/
124int psci_validate_power_state(unsigned int power_state,
125 psci_power_state_t *state_info)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100126{
Soby Mathew981487a2015-07-13 14:10:57 +0100127 /* Check SBZ bits in power state are zero */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100128 if (psci_check_power_state(power_state) != 0U)
Soby Mathew981487a2015-07-13 14:10:57 +0100129 return PSCI_E_INVALID_PARAMS;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100130
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100131 assert(psci_plat_pm_ops->validate_power_state != NULL);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100132
Soby Mathew981487a2015-07-13 14:10:57 +0100133 /* Validate the power_state using platform pm_ops */
134 return psci_plat_pm_ops->validate_power_state(power_state, state_info);
135}
Achin Guptaf6b9e992014-07-31 11:19:11 +0100136
Soby Mathew981487a2015-07-13 14:10:57 +0100137/******************************************************************************
138 * This function retrieves the `psci_power_state_t` for system suspend from
139 * the platform.
140 *****************************************************************************/
141void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info)
142{
143 /*
144 * Assert that the required pm_ops hook is implemented to ensure that
145 * the capability detected during psci_setup() is valid.
146 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100147 assert(psci_plat_pm_ops->get_sys_suspend_power_state != NULL);
Soby Mathew981487a2015-07-13 14:10:57 +0100148
149 /*
150 * Query the platform for the power_state required for system suspend
151 */
152 psci_plat_pm_ops->get_sys_suspend_power_state(state_info);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100153}
154
155/*******************************************************************************
Soby Mathew96168382014-12-17 14:47:57 +0000156 * This function verifies that the all the other cores in the system have been
157 * turned OFF and the current CPU is the last running CPU in the system.
158 * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false)
159 * otherwise.
160 ******************************************************************************/
161unsigned int psci_is_last_on_cpu(void)
162{
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300163 unsigned int cpu_idx, my_idx = plat_my_core_pos();
Soby Mathew96168382014-12-17 14:47:57 +0000164
Pankaj Gupta02c35682019-10-15 15:44:45 +0530165 for (cpu_idx = 0; cpu_idx < psci_plat_core_count;
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300166 cpu_idx++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100167 if (cpu_idx == my_idx) {
168 assert(psci_get_aff_info_state() == AFF_STATE_ON);
Soby Mathew96168382014-12-17 14:47:57 +0000169 continue;
170 }
171
Soby Mathew981487a2015-07-13 14:10:57 +0100172 if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF)
Soby Mathew96168382014-12-17 14:47:57 +0000173 return 0;
174 }
175
176 return 1;
177}
178
179/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100180 * Routine to return the maximum power level to traverse to after a cpu has
181 * been physically powered up. It is expected to be called immediately after
182 * reset from assembler code.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100183 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100184static unsigned int get_power_on_target_pwrlvl(void)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100185{
Soby Mathew011ca182015-07-29 17:05:03 +0100186 unsigned int pwrlvl;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100187
188 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100189 * Assume that this cpu was suspended and retrieve its target power
190 * level. If it is invalid then it could only have been turned off
191 * earlier. PLAT_MAX_PWR_LVL will be the highest power level a
192 * cpu can be turned off to.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100193 */
Soby Mathew981487a2015-07-13 14:10:57 +0100194 pwrlvl = psci_get_suspend_pwrlvl();
Soby Mathew011ca182015-07-29 17:05:03 +0100195 if (pwrlvl == PSCI_INVALID_PWR_LVL)
Soby Mathew981487a2015-07-13 14:10:57 +0100196 pwrlvl = PLAT_MAX_PWR_LVL;
Deepika Bhavnani523024c2019-08-17 01:10:02 +0300197 assert(pwrlvl < PSCI_INVALID_PWR_LVL);
Soby Mathew981487a2015-07-13 14:10:57 +0100198 return pwrlvl;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100199}
200
Soby Mathew981487a2015-07-13 14:10:57 +0100201/******************************************************************************
202 * Helper function to update the requested local power state array. This array
203 * does not store the requested state for the CPU power level. Hence an
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300204 * assertion is added to prevent us from accessing the CPU power level.
Soby Mathew981487a2015-07-13 14:10:57 +0100205 *****************************************************************************/
206static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
207 unsigned int cpu_idx,
208 plat_local_state_t req_pwr_state)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100209{
Soby Mathew981487a2015-07-13 14:10:57 +0100210 assert(pwrlvl > PSCI_CPU_PWR_LVL);
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300211 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
Pankaj Gupta02c35682019-10-15 15:44:45 +0530212 (cpu_idx < psci_plat_core_count)) {
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300213 psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
214 }
Achin Guptaf6b9e992014-07-31 11:19:11 +0100215}
216
Soby Mathew981487a2015-07-13 14:10:57 +0100217/******************************************************************************
218 * This function initializes the psci_req_local_pwr_states.
219 *****************************************************************************/
Daniel Boulby5753e492018-09-20 14:12:46 +0100220void __init psci_init_req_local_pwr_states(void)
Achin Guptaa45e3972013-12-05 15:10:48 +0000221{
Soby Mathew981487a2015-07-13 14:10:57 +0100222 /* Initialize the requested state of all non CPU power domains as OFF */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100223 unsigned int pwrlvl;
Pankaj Gupta02c35682019-10-15 15:44:45 +0530224 unsigned int core;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100225
226 for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) {
Pankaj Gupta02c35682019-10-15 15:44:45 +0530227 for (core = 0; core < psci_plat_core_count; core++) {
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100228 psci_req_local_pwr_states[pwrlvl][core] =
229 PLAT_MAX_OFF_STATE;
230 }
231 }
Soby Mathew981487a2015-07-13 14:10:57 +0100232}
Achin Guptaa45e3972013-12-05 15:10:48 +0000233
Soby Mathew981487a2015-07-13 14:10:57 +0100234/******************************************************************************
235 * Helper function to return a reference to an array containing the local power
236 * states requested by each cpu for a power domain at 'pwrlvl'. The size of the
237 * array will be the number of cpu power domains of which this power domain is
238 * an ancestor. These requested states will be used to determine a suitable
239 * target state for this power domain during psci state coordination. An
240 * assertion is added to prevent us from accessing the CPU power level.
241 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100242static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl,
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300243 unsigned int cpu_idx)
Soby Mathew981487a2015-07-13 14:10:57 +0100244{
245 assert(pwrlvl > PSCI_CPU_PWR_LVL);
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100246
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300247 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
Pankaj Gupta02c35682019-10-15 15:44:45 +0530248 (cpu_idx < psci_plat_core_count)) {
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300249 return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
250 } else
251 return NULL;
Soby Mathew981487a2015-07-13 14:10:57 +0100252}
Achin Guptaa45e3972013-12-05 15:10:48 +0000253
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000254/*
255 * psci_non_cpu_pd_nodes can be placed either in normal memory or coherent
256 * memory.
257 *
258 * With !USE_COHERENT_MEM, psci_non_cpu_pd_nodes is placed in normal memory,
259 * it's accessed by both cached and non-cached participants. To serve the common
260 * minimum, perform a cache flush before read and after write so that non-cached
261 * participants operate on latest data in main memory.
262 *
263 * When USE_COHERENT_MEM is used, psci_non_cpu_pd_nodes is placed in coherent
264 * memory. With HW_ASSISTED_COHERENCY, all PSCI participants are cache-coherent.
265 * In both cases, no cache operations are required.
266 */
267
268/*
269 * Retrieve local state of non-CPU power domain node from a non-cached CPU,
270 * after any required cache maintenance operation.
271 */
272static plat_local_state_t get_non_cpu_pd_node_local_state(
273 unsigned int parent_idx)
274{
Andrew F. Davise6f28fa2018-08-30 12:13:57 -0500275#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000276 flush_dcache_range(
277 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
278 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
279#endif
280 return psci_non_cpu_pd_nodes[parent_idx].local_state;
281}
282
283/*
284 * Update local state of non-CPU power domain node from a cached CPU; perform
285 * any required cache maintenance operation afterwards.
286 */
287static void set_non_cpu_pd_node_local_state(unsigned int parent_idx,
288 plat_local_state_t state)
289{
290 psci_non_cpu_pd_nodes[parent_idx].local_state = state;
Andrew F. Davise6f28fa2018-08-30 12:13:57 -0500291#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000292 flush_dcache_range(
293 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
294 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
295#endif
296}
297
Soby Mathew981487a2015-07-13 14:10:57 +0100298/******************************************************************************
299 * Helper function to return the current local power state of each power domain
300 * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This
301 * function will be called after a cpu is powered on to find the local state
302 * each power domain has emerged from.
303 *****************************************************************************/
Achin Gupta9b2bf252016-06-28 16:46:15 +0100304void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
305 psci_power_state_t *target_state)
Soby Mathew981487a2015-07-13 14:10:57 +0100306{
Soby Mathew011ca182015-07-29 17:05:03 +0100307 unsigned int parent_idx, lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100308 plat_local_state_t *pd_state = target_state->pwr_domain_state;
309
310 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state();
311 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
312
313 /* Copy the local power state from node to state_info */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100314 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000315 pd_state[lvl] = get_non_cpu_pd_node_local_state(parent_idx);
Soby Mathew981487a2015-07-13 14:10:57 +0100316 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
317 }
318
319 /* Set the the higher levels to RUN */
320 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
321 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
322}
323
324/******************************************************************************
325 * Helper function to set the target local power state that each power domain
326 * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will
327 * enter. This function will be called after coordination of requested power
328 * states has been done for each power level.
329 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100330static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100331 const psci_power_state_t *target_state)
332{
Soby Mathew011ca182015-07-29 17:05:03 +0100333 unsigned int parent_idx, lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100334 const plat_local_state_t *pd_state = target_state->pwr_domain_state;
335
336 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]);
Achin Guptaa45e3972013-12-05 15:10:48 +0000337
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100338 /*
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000339 * Need to flush as local_state might be accessed with Data Cache
Soby Mathew981487a2015-07-13 14:10:57 +0100340 * disabled during power on
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100341 */
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000342 psci_flush_cpu_data(psci_svc_cpu_data.local_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100343
344 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
345
346 /* Copy the local_state from state_info */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100347 for (lvl = 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000348 set_non_cpu_pd_node_local_state(parent_idx, pd_state[lvl]);
Soby Mathew981487a2015-07-13 14:10:57 +0100349 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
350 }
Achin Guptaa45e3972013-12-05 15:10:48 +0000351}
352
Soby Mathew981487a2015-07-13 14:10:57 +0100353
Achin Guptaa45e3972013-12-05 15:10:48 +0000354/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100355 * PSCI helper function to get the parent nodes corresponding to a cpu_index.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100356 ******************************************************************************/
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300357void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
Soby Mathew011ca182015-07-29 17:05:03 +0100358 unsigned int end_lvl,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100359 unsigned int *node_index)
Soby Mathew981487a2015-07-13 14:10:57 +0100360{
361 unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node;
Varun Wadekar66231d12017-06-07 09:57:42 -0700362 unsigned int i;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100363 unsigned int *node = node_index;
Soby Mathew981487a2015-07-13 14:10:57 +0100364
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100365 for (i = PSCI_CPU_PWR_LVL + 1U; i <= end_lvl; i++) {
366 *node = parent_node;
367 node++;
Soby Mathew981487a2015-07-13 14:10:57 +0100368 parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node;
369 }
370}
371
372/******************************************************************************
373 * This function is invoked post CPU power up and initialization. It sets the
374 * affinity info state, target power state and requested power state for the
375 * current CPU and all its ancestor power domains to RUN.
376 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100377void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl)
Soby Mathew981487a2015-07-13 14:10:57 +0100378{
Soby Mathew011ca182015-07-29 17:05:03 +0100379 unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100380 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
381
382 /* Reset the local_state to RUN for the non cpu power domains. */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100383 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000384 set_non_cpu_pd_node_local_state(parent_idx,
385 PSCI_LOCAL_STATE_RUN);
Soby Mathew981487a2015-07-13 14:10:57 +0100386 psci_set_req_local_pwr_state(lvl,
387 cpu_idx,
388 PSCI_LOCAL_STATE_RUN);
389 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
390 }
391
392 /* Set the affinity info state to ON */
393 psci_set_aff_info_state(AFF_STATE_ON);
394
395 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000396 psci_flush_cpu_data(psci_svc_cpu_data);
Soby Mathew981487a2015-07-13 14:10:57 +0100397}
398
399/******************************************************************************
400 * This function is passed the local power states requested for each power
401 * domain (state_info) between the current CPU domain and its ancestors until
402 * the target power level (end_pwrlvl). It updates the array of requested power
403 * states with this information.
404 *
405 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it
406 * retrieves the states requested by all the cpus of which the power domain at
407 * that level is an ancestor. It passes this information to the platform to
408 * coordinate and return the target power state. If the target state for a level
409 * is RUN then subsequent levels are not considered. At the CPU level, state
410 * coordination is not required. Hence, the requested and the target states are
411 * the same.
412 *
413 * The 'state_info' is updated with the target state for each level between the
414 * CPU and the 'end_pwrlvl' and returned to the caller.
415 *
416 * This function will only be invoked with data cache enabled and while
417 * powering down a core.
418 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100419void psci_do_state_coordination(unsigned int end_pwrlvl,
420 psci_power_state_t *state_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100421{
Soby Mathew981487a2015-07-13 14:10:57 +0100422 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos();
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300423 unsigned int start_idx;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100424 unsigned int ncpus;
Soby Mathew981487a2015-07-13 14:10:57 +0100425 plat_local_state_t target_state, *req_states;
426
Soby Mathew1298e692016-02-02 14:23:10 +0000427 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
Soby Mathew981487a2015-07-13 14:10:57 +0100428 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
429
430 /* For level 0, the requested state will be equivalent
431 to target state */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100432 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100433
434 /* First update the requested power state */
435 psci_set_req_local_pwr_state(lvl, cpu_idx,
436 state_info->pwr_domain_state[lvl]);
437
438 /* Get the requested power states for this power level */
439 start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx;
440 req_states = psci_get_req_local_pwr_states(lvl, start_idx);
441
442 /*
443 * Let the platform coordinate amongst the requested states at
444 * this power level and return the target local power state.
445 */
446 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus;
447 target_state = plat_get_target_pwr_state(lvl,
448 req_states,
449 ncpus);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100450
Soby Mathew981487a2015-07-13 14:10:57 +0100451 state_info->pwr_domain_state[lvl] = target_state;
452
453 /* Break early if the negotiated target power state is RUN */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100454 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0)
Soby Mathew981487a2015-07-13 14:10:57 +0100455 break;
456
457 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
458 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100459
460 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100461 * This is for cases when we break out of the above loop early because
462 * the target power state is RUN at a power level < end_pwlvl.
463 * We update the requested power state from state_info and then
464 * set the target state as RUN.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100465 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100466 for (lvl = lvl + 1U; lvl <= end_pwrlvl; lvl++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100467 psci_set_req_local_pwr_state(lvl, cpu_idx,
468 state_info->pwr_domain_state[lvl]);
469 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100470
Soby Mathew981487a2015-07-13 14:10:57 +0100471 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100472
Soby Mathew981487a2015-07-13 14:10:57 +0100473 /* Update the target state in the power domain nodes */
474 psci_set_target_local_pwr_states(end_pwrlvl, state_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100475}
476
Soby Mathew981487a2015-07-13 14:10:57 +0100477/******************************************************************************
478 * This function validates a suspend request by making sure that if a standby
479 * state is requested then no power level is turned off and the highest power
480 * level is placed in a standby/retention state.
481 *
482 * It also ensures that the state level X will enter is not shallower than the
483 * state level X + 1 will enter.
484 *
485 * This validation will be enabled only for DEBUG builds as the platform is
486 * expected to perform these validations as well.
487 *****************************************************************************/
488int psci_validate_suspend_req(const psci_power_state_t *state_info,
489 unsigned int is_power_down_state)
Achin Gupta0959db52013-12-02 17:33:04 +0000490{
Soby Mathew981487a2015-07-13 14:10:57 +0100491 unsigned int max_off_lvl, target_lvl, max_retn_lvl;
492 plat_local_state_t state;
493 plat_local_state_type_t req_state_type, deepest_state_type;
494 int i;
Achin Gupta0959db52013-12-02 17:33:04 +0000495
Soby Mathew981487a2015-07-13 14:10:57 +0100496 /* Find the target suspend power level */
497 target_lvl = psci_find_target_suspend_lvl(state_info);
Soby Mathew011ca182015-07-29 17:05:03 +0100498 if (target_lvl == PSCI_INVALID_PWR_LVL)
Achin Gupta0959db52013-12-02 17:33:04 +0000499 return PSCI_E_INVALID_PARAMS;
500
Soby Mathew981487a2015-07-13 14:10:57 +0100501 /* All power domain levels are in a RUN state to begin with */
502 deepest_state_type = STATE_TYPE_RUN;
503
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100504 for (i = (int) target_lvl; i >= (int) PSCI_CPU_PWR_LVL; i--) {
Soby Mathew981487a2015-07-13 14:10:57 +0100505 state = state_info->pwr_domain_state[i];
506 req_state_type = find_local_state_type(state);
507
508 /*
509 * While traversing from the highest power level to the lowest,
510 * the state requested for lower levels has to be the same or
511 * deeper i.e. equal to or greater than the state at the higher
512 * levels. If this condition is true, then the requested state
513 * becomes the deepest state encountered so far.
514 */
515 if (req_state_type < deepest_state_type)
516 return PSCI_E_INVALID_PARAMS;
517 deepest_state_type = req_state_type;
518 }
519
520 /* Find the highest off power level */
521 max_off_lvl = psci_find_max_off_lvl(state_info);
522
523 /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */
Soby Mathew011ca182015-07-29 17:05:03 +0100524 max_retn_lvl = PSCI_INVALID_PWR_LVL;
Soby Mathew981487a2015-07-13 14:10:57 +0100525 if (target_lvl != max_off_lvl)
526 max_retn_lvl = target_lvl;
527
528 /*
529 * If this is not a request for a power down state then max off level
530 * has to be invalid and max retention level has to be a valid power
531 * level.
532 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100533 if ((is_power_down_state == 0U) &&
534 ((max_off_lvl != PSCI_INVALID_PWR_LVL) ||
535 (max_retn_lvl == PSCI_INVALID_PWR_LVL)))
Achin Gupta0959db52013-12-02 17:33:04 +0000536 return PSCI_E_INVALID_PARAMS;
537
538 return PSCI_E_SUCCESS;
539}
540
Soby Mathew981487a2015-07-13 14:10:57 +0100541/******************************************************************************
542 * This function finds the highest power level which will be powered down
543 * amongst all the power levels specified in the 'state_info' structure
544 *****************************************************************************/
545unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info)
Achin Guptacab78e42014-07-28 00:09:01 +0100546{
Soby Mathew981487a2015-07-13 14:10:57 +0100547 int i;
Achin Guptacab78e42014-07-28 00:09:01 +0100548
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100549 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
550 if (is_local_state_off(state_info->pwr_domain_state[i]) != 0)
551 return (unsigned int) i;
Soby Mathew981487a2015-07-13 14:10:57 +0100552 }
553
Soby Mathew011ca182015-07-29 17:05:03 +0100554 return PSCI_INVALID_PWR_LVL;
Soby Mathew981487a2015-07-13 14:10:57 +0100555}
556
557/******************************************************************************
558 * This functions finds the level of the highest power domain which will be
559 * placed in a low power state during a suspend operation.
560 *****************************************************************************/
561unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info)
562{
563 int i;
564
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100565 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
566 if (is_local_state_run(state_info->pwr_domain_state[i]) == 0)
567 return (unsigned int) i;
Achin Guptacab78e42014-07-28 00:09:01 +0100568 }
Soby Mathew981487a2015-07-13 14:10:57 +0100569
Soby Mathew011ca182015-07-29 17:05:03 +0100570 return PSCI_INVALID_PWR_LVL;
Achin Guptacab78e42014-07-28 00:09:01 +0100571}
572
573/*******************************************************************************
Andrew F. Davis74e89782019-06-04 10:46:54 -0400574 * This function is passed the highest level in the topology tree that the
575 * operation should be applied to and a list of node indexes. It picks up locks
576 * from the node index list in order of increasing power domain level in the
577 * range specified.
Achin Gupta0959db52013-12-02 17:33:04 +0000578 ******************************************************************************/
Andrew F. Davis74e89782019-06-04 10:46:54 -0400579void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl,
580 const unsigned int *parent_nodes)
Achin Gupta0959db52013-12-02 17:33:04 +0000581{
Andrew F. Davis74e89782019-06-04 10:46:54 -0400582 unsigned int parent_idx;
Soby Mathew011ca182015-07-29 17:05:03 +0100583 unsigned int level;
Achin Gupta0959db52013-12-02 17:33:04 +0000584
Soby Mathew981487a2015-07-13 14:10:57 +0100585 /* No locking required for level 0. Hence start locking from level 1 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100586 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) {
Andrew F. Davis74e89782019-06-04 10:46:54 -0400587 parent_idx = parent_nodes[level - 1U];
Soby Mathew981487a2015-07-13 14:10:57 +0100588 psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]);
Achin Gupta0959db52013-12-02 17:33:04 +0000589 }
590}
591
592/*******************************************************************************
Andrew F. Davis74e89782019-06-04 10:46:54 -0400593 * This function is passed the highest level in the topology tree that the
594 * operation should be applied to and a list of node indexes. It releases the
595 * locks in order of decreasing power domain level in the range specified.
Achin Gupta0959db52013-12-02 17:33:04 +0000596 ******************************************************************************/
Andrew F. Davis74e89782019-06-04 10:46:54 -0400597void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
598 const unsigned int *parent_nodes)
Achin Gupta0959db52013-12-02 17:33:04 +0000599{
Andrew F. Davis74e89782019-06-04 10:46:54 -0400600 unsigned int parent_idx;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100601 unsigned int level;
Achin Gupta0959db52013-12-02 17:33:04 +0000602
Soby Mathew981487a2015-07-13 14:10:57 +0100603 /* Unlock top down. No unlocking required for level 0. */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100604 for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1U; level--) {
605 parent_idx = parent_nodes[level - 1U];
Soby Mathew981487a2015-07-13 14:10:57 +0100606 psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]);
Achin Gupta0959db52013-12-02 17:33:04 +0000607 }
608}
609
610/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100611 * Simple routine to determine whether a mpidr is valid or not.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100612 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100613int psci_validate_mpidr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100614{
Soby Mathew981487a2015-07-13 14:10:57 +0100615 if (plat_core_pos_by_mpidr(mpidr) < 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100616 return PSCI_E_INVALID_PARAMS;
Soby Mathew981487a2015-07-13 14:10:57 +0100617
618 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100619}
620
621/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100622 * This function determines the full entrypoint information for the requested
Soby Mathew8595b872015-01-06 15:36:38 +0000623 * PSCI entrypoint on power on/resume and returns it.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100624 ******************************************************************************/
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700625#ifdef __aarch64__
Soby Mathewf1f97a12015-07-15 12:13:26 +0100626static int psci_get_ns_ep_info(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100627 uintptr_t entrypoint,
628 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100629{
Soby Mathewa0fedc42016-06-16 14:52:04 +0100630 u_register_t ep_attr, sctlr;
Soby Mathew011ca182015-07-29 17:05:03 +0100631 unsigned int daif, ee, mode;
Soby Mathewa0fedc42016-06-16 14:52:04 +0100632 u_register_t ns_scr_el3 = read_scr_el3();
633 u_register_t ns_sctlr_el1 = read_sctlr_el1();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100634
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100635 sctlr = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
636 read_sctlr_el2() : ns_sctlr_el1;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100637 ee = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100638
Andrew Thoelke4e126072014-06-04 21:10:52 +0100639 ep_attr = NON_SECURE | EP_ST_DISABLE;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100640 if ((sctlr & SCTLR_EE_BIT) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100641 ep_attr |= EP_EE_BIG;
642 ee = 1;
643 }
Soby Mathew8595b872015-01-06 15:36:38 +0000644 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100645
Soby Mathew8595b872015-01-06 15:36:38 +0000646 ep->pc = entrypoint;
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000647 zeromem(&ep->args, sizeof(ep->args));
Soby Mathew8595b872015-01-06 15:36:38 +0000648 ep->args.arg0 = context_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100649
650 /*
651 * Figure out whether the cpu enters the non-secure address space
652 * in aarch32 or aarch64
653 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100654 if ((ns_scr_el3 & SCR_RW_BIT) != 0U) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100655
656 /*
657 * Check whether a Thumb entry point has been provided for an
658 * aarch64 EL
659 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100660 if ((entrypoint & 0x1UL) != 0UL)
Soby Mathewf1f97a12015-07-15 12:13:26 +0100661 return PSCI_E_INVALID_ADDRESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100662
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100663 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? MODE_EL2 : MODE_EL1;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100664
Soby Mathew8595b872015-01-06 15:36:38 +0000665 ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100666 } else {
667
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100668 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
669 MODE32_hyp : MODE32_svc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100670
671 /*
672 * TODO: Choose async. exception bits if HYP mode is not
673 * implemented according to the values of SCR.{AW, FW} bits
674 */
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100675 daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
676
Soby Mathew8595b872015-01-06 15:36:38 +0000677 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100678 }
679
Andrew Thoelke4e126072014-06-04 21:10:52 +0100680 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100681}
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700682#else /* !__aarch64__ */
683static int psci_get_ns_ep_info(entry_point_info_t *ep,
684 uintptr_t entrypoint,
685 u_register_t context_id)
686{
687 u_register_t ep_attr;
688 unsigned int aif, ee, mode;
689 u_register_t scr = read_scr();
690 u_register_t ns_sctlr, sctlr;
691
692 /* Switch to non secure state */
693 write_scr(scr | SCR_NS_BIT);
694 isb();
695 ns_sctlr = read_sctlr();
696
697 sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr;
698
699 /* Return to original state */
700 write_scr(scr);
701 isb();
702 ee = 0;
703
704 ep_attr = NON_SECURE | EP_ST_DISABLE;
705 if (sctlr & SCTLR_EE_BIT) {
706 ep_attr |= EP_EE_BIG;
707 ee = 1;
708 }
709 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
710
711 ep->pc = entrypoint;
712 zeromem(&ep->args, sizeof(ep->args));
713 ep->args.arg0 = context_id;
714
715 mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
716
717 /*
718 * TODO: Choose async. exception bits if HYP mode is not
719 * implemented according to the values of SCR.{AW, FW} bits
720 */
721 aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT;
722
723 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif);
724
725 return PSCI_E_SUCCESS;
726}
727
728#endif /* __aarch64__ */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100729
730/*******************************************************************************
Soby Mathewf1f97a12015-07-15 12:13:26 +0100731 * This function validates the entrypoint with the platform layer if the
732 * appropriate pm_ops hook is exported by the platform and returns the
733 * 'entry_point_info'.
734 ******************************************************************************/
735int psci_validate_entry_point(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100736 uintptr_t entrypoint,
737 u_register_t context_id)
Soby Mathewf1f97a12015-07-15 12:13:26 +0100738{
739 int rc;
740
741 /* Validate the entrypoint using platform psci_ops */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100742 if (psci_plat_pm_ops->validate_ns_entrypoint != NULL) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100743 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint);
744 if (rc != PSCI_E_SUCCESS)
745 return PSCI_E_INVALID_ADDRESS;
746 }
747
748 /*
749 * Verify and derive the re-entry information for
750 * the non-secure world from the non-secure state from
751 * where this call originated.
752 */
753 rc = psci_get_ns_ep_info(ep, entrypoint, context_id);
754 return rc;
755}
756
757/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100758 * Generic handler which is called when a cpu is physically powered on. It
Soby Mathew981487a2015-07-13 14:10:57 +0100759 * traverses the node information and finds the highest power level powered
760 * off and performs generic, architectural, platform setup and state management
761 * to power on that power level and power levels below it.
762 * e.g. For a cpu that's been powered on, it will call the platform specific
763 * code to enable the gic cpu interface and for a cluster it will enable
764 * coherency at the interconnect level in addition to gic cpu interface.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100765 ******************************************************************************/
Soby Mathewd0194872016-04-29 19:01:30 +0100766void psci_warmboot_entrypoint(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100767{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100768 unsigned int end_pwrlvl;
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300769 unsigned int cpu_idx = plat_my_core_pos();
Andrew F. Davis74e89782019-06-04 10:46:54 -0400770 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
Soby Mathew981487a2015-07-13 14:10:57 +0100771 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
Achin Gupta4f6ad662013-10-25 09:08:21 +0100772
Achin Gupta4f6ad662013-10-25 09:08:21 +0100773 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100774 * Verify that we have been explicitly turned ON or resumed from
775 * suspend.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100776 */
Soby Mathew981487a2015-07-13 14:10:57 +0100777 if (psci_get_aff_info_state() == AFF_STATE_OFF) {
778 ERROR("Unexpected affinity info state");
James Morrissey40a6f642014-02-10 14:24:36 +0000779 panic();
Soby Mathew981487a2015-07-13 14:10:57 +0100780 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100781
782 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100783 * Get the maximum power domain level to traverse to after this cpu
784 * has been physically powered up.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100785 */
Soby Mathew981487a2015-07-13 14:10:57 +0100786 end_pwrlvl = get_power_on_target_pwrlvl();
Achin Guptaf6b9e992014-07-31 11:19:11 +0100787
Andrew F. Davis74e89782019-06-04 10:46:54 -0400788 /* Get the parent nodes */
789 psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes);
790
Achin Guptaf6b9e992014-07-31 11:19:11 +0100791 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100792 * This function acquires the lock corresponding to each power level so
793 * that by the time all locks are taken, the system topology is snapshot
794 * and state management can be done safely.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100795 */
Andrew F. Davis74e89782019-06-04 10:46:54 -0400796 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100797
Soby Mathew8336f682017-10-16 15:19:31 +0100798 psci_get_target_local_pwr_states(end_pwrlvl, &state_info);
799
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100800#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +0000801 plat_psci_stat_accounting_stop(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100802#endif
803
Achin Gupta4f6ad662013-10-25 09:08:21 +0100804 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100805 * This CPU could be resuming from suspend or it could have just been
806 * turned on. To distinguish between these 2 cases, we examine the
807 * affinity state of the CPU:
808 * - If the affinity state is ON_PENDING then it has just been
809 * turned on.
810 * - Else it is resuming from suspend.
811 *
812 * Depending on the type of warm reset identified, choose the right set
813 * of power management handler and perform the generic, architecture
814 * and platform specific handling.
Achin Guptacab78e42014-07-28 00:09:01 +0100815 */
Soby Mathew981487a2015-07-13 14:10:57 +0100816 if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING)
817 psci_cpu_on_finish(cpu_idx, &state_info);
818 else
819 psci_cpu_suspend_finish(cpu_idx, &state_info);
Achin Guptacab78e42014-07-28 00:09:01 +0100820
821 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100822 * Set the requested and target state of this CPU and all the higher
823 * power domains which are ancestors of this CPU to run.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100824 */
Soby Mathew981487a2015-07-13 14:10:57 +0100825 psci_set_pwr_domains_to_run(end_pwrlvl);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100826
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100827#if ENABLE_PSCI_STAT
828 /*
829 * Update PSCI stats.
830 * Caches are off when writing stats data on the power down path.
831 * Since caches are now enabled, it's necessary to do cache
832 * maintenance before reading that same data.
833 */
dp-arm66abfbe2017-01-31 13:01:04 +0000834 psci_stats_update_pwr_up(end_pwrlvl, &state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100835#endif
836
Achin Guptaf6b9e992014-07-31 11:19:11 +0100837 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100838 * This loop releases the lock corresponding to each power level
Achin Gupta0959db52013-12-02 17:33:04 +0000839 * in the reverse order to which they were acquired.
840 */
Andrew F. Davis74e89782019-06-04 10:46:54 -0400841 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100842}
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000843
844/*******************************************************************************
845 * This function initializes the set of hooks that PSCI invokes as part of power
846 * management operation. The power management hooks are expected to be provided
847 * by the SPD, after it finishes all its initialization
848 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100849void psci_register_spd_pm_hook(const spd_pm_ops_t *pm)
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000850{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100851 assert(pm != NULL);
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000852 psci_spd_pm = pm;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000853
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100854 if (pm->svc_migrate != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000855 psci_caps |= define_psci_cap(PSCI_MIG_AARCH64);
856
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100857 if (pm->svc_migrate_info != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000858 psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64)
859 | define_psci_cap(PSCI_MIG_INFO_TYPE);
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000860}
Juan Castillo4dc4a472014-08-12 11:17:06 +0100861
862/*******************************************************************************
Soby Mathew110fe362014-10-23 10:35:34 +0100863 * This function invokes the migrate info hook in the spd_pm_ops. It performs
864 * the necessary return value validation. If the Secure Payload is UP and
865 * migrate capable, it returns the mpidr of the CPU on which the Secure payload
866 * is resident through the mpidr parameter. Else the value of the parameter on
867 * return is undefined.
868 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100869int psci_spd_migrate_info(u_register_t *mpidr)
Soby Mathew110fe362014-10-23 10:35:34 +0100870{
871 int rc;
872
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100873 if ((psci_spd_pm == NULL) || (psci_spd_pm->svc_migrate_info == NULL))
Soby Mathew110fe362014-10-23 10:35:34 +0100874 return PSCI_E_NOT_SUPPORTED;
875
876 rc = psci_spd_pm->svc_migrate_info(mpidr);
877
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100878 assert((rc == PSCI_TOS_UP_MIG_CAP) || (rc == PSCI_TOS_NOT_UP_MIG_CAP) ||
879 (rc == PSCI_TOS_NOT_PRESENT_MP) || (rc == PSCI_E_NOT_SUPPORTED));
Soby Mathew110fe362014-10-23 10:35:34 +0100880
881 return rc;
882}
883
884
885/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100886 * This function prints the state of all power domains present in the
Juan Castillo4dc4a472014-08-12 11:17:06 +0100887 * system
888 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100889void psci_print_power_domain_map(void)
Juan Castillo4dc4a472014-08-12 11:17:06 +0100890{
891#if LOG_LEVEL >= LOG_LEVEL_INFO
Pankaj Gupta02c35682019-10-15 15:44:45 +0530892 unsigned int idx;
Soby Mathew981487a2015-07-13 14:10:57 +0100893 plat_local_state_t state;
894 plat_local_state_type_t state_type;
895
Juan Castillo4dc4a472014-08-12 11:17:06 +0100896 /* This array maps to the PSCI_STATE_X definitions in psci.h */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100897 static const char * const psci_state_type_str[] = {
Juan Castillo4dc4a472014-08-12 11:17:06 +0100898 "ON",
Soby Mathew981487a2015-07-13 14:10:57 +0100899 "RETENTION",
Juan Castillo4dc4a472014-08-12 11:17:06 +0100900 "OFF",
Juan Castillo4dc4a472014-08-12 11:17:06 +0100901 };
902
Soby Mathew981487a2015-07-13 14:10:57 +0100903 INFO("PSCI Power Domain Map:\n");
Pankaj Gupta02c35682019-10-15 15:44:45 +0530904 for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - psci_plat_core_count);
Soby Mathew981487a2015-07-13 14:10:57 +0100905 idx++) {
906 state_type = find_local_state_type(
907 psci_non_cpu_pd_nodes[idx].local_state);
908 INFO(" Domain Node : Level %u, parent_node %d,"
909 " State %s (0x%x)\n",
910 psci_non_cpu_pd_nodes[idx].level,
911 psci_non_cpu_pd_nodes[idx].parent_node,
912 psci_state_type_str[state_type],
913 psci_non_cpu_pd_nodes[idx].local_state);
914 }
915
Pankaj Gupta02c35682019-10-15 15:44:45 +0530916 for (idx = 0; idx < psci_plat_core_count; idx++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100917 state = psci_get_cpu_local_state_by_idx(idx);
918 state_type = find_local_state_type(state);
Soby Mathewa0fedc42016-06-16 14:52:04 +0100919 INFO(" CPU Node : MPID 0x%llx, parent_node %d,"
Soby Mathew981487a2015-07-13 14:10:57 +0100920 " State %s (0x%x)\n",
Soby Mathewa0fedc42016-06-16 14:52:04 +0100921 (unsigned long long)psci_cpu_pd_nodes[idx].mpidr,
Soby Mathew981487a2015-07-13 14:10:57 +0100922 psci_cpu_pd_nodes[idx].parent_node,
923 psci_state_type_str[state_type],
924 psci_get_cpu_local_state_by_idx(idx));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100925 }
926#endif
927}
Soby Mathew981487a2015-07-13 14:10:57 +0100928
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000929/******************************************************************************
930 * Return whether any secondaries were powered up with CPU_ON call. A CPU that
931 * have ever been powered up would have set its MPDIR value to something other
932 * than PSCI_INVALID_MPIDR. Note that MPDIR isn't reset back to
933 * PSCI_INVALID_MPIDR when a CPU is powered down later, so the return value is
934 * meaningful only when called on the primary CPU during early boot.
935 *****************************************************************************/
936int psci_secondaries_brought_up(void)
937{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100938 unsigned int idx, n_valid = 0U;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000939
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100940 for (idx = 0U; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) {
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000941 if (psci_cpu_pd_nodes[idx].mpidr != PSCI_INVALID_MPIDR)
942 n_valid++;
943 }
944
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100945 assert(n_valid > 0U);
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000946
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100947 return (n_valid > 1U) ? 1 : 0;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000948}
949
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000950/*******************************************************************************
951 * Initiate power down sequence, by calling power down operations registered for
952 * this CPU.
953 ******************************************************************************/
954void psci_do_pwrdown_sequence(unsigned int power_level)
955{
956#if HW_ASSISTED_COHERENCY
957 /*
958 * With hardware-assisted coherency, the CPU drivers only initiate the
959 * power down sequence, without performing cache-maintenance operations
Andrew F. Davis564f9542018-08-30 12:08:01 -0500960 * in software. Data caches enabled both before and after this call.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000961 */
962 prepare_cpu_pwr_dwn(power_level);
963#else
964 /*
965 * Without hardware-assisted coherency, the CPU drivers disable data
Andrew F. Davis564f9542018-08-30 12:08:01 -0500966 * caches, then perform cache-maintenance operations in software.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000967 *
Andrew F. Davis564f9542018-08-30 12:08:01 -0500968 * This also calls prepare_cpu_pwr_dwn() to initiate power down
969 * sequence, but that function will return with data caches disabled.
970 * We must ensure that the stack memory is flushed out to memory before
971 * we start popping from it again.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000972 */
973 psci_do_pwrdown_cache_maintenance(power_level);
974#endif
975}