blob: b6c2d81429041215586318b7b8707da3fc897399 [file] [log] [blame]
Tejas Patel354fe572018-12-14 00:55:37 -08001/*
2 * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
Jay Buddhabhatti26e138a2022-12-21 23:03:35 -08003 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Tejas Patel354fe572018-12-14 00:55:37 -08004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/* Versal PM nodes enums and defines */
9
10#ifndef PM_NODE_H
11#define PM_NODE_H
12
13/*********************************************************************
14 * Macro definitions
15 ********************************************************************/
16
17#define NODE_CLASS_SHIFT 26U
18#define NODE_SUBCLASS_SHIFT 20U
19#define NODE_TYPE_SHIFT 14U
20#define NODE_INDEX_SHIFT 0U
Jay Buddhabhattif2f84b32023-02-09 22:56:53 -080021#define NODE_CLASS_MASK_BITS GENMASK_32(5, 0)
22#define NODE_SUBCLASS_MASK_BITS GENMASK_32(5, 0)
23#define NODE_TYPE_MASK_BITS GENMASK_32(5, 0)
24#define NODE_INDEX_MASK_BITS GENMASK_32(13, 0)
Tejas Patel354fe572018-12-14 00:55:37 -080025#define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
26#define NODE_SUBCLASS_MASK (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT)
27#define NODE_TYPE_MASK (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT)
28#define NODE_INDEX_MASK (NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT)
29
30#define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \
31 ((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
32 (((SUBCLASS) & NODE_SUBCLASS_MASK_BITS) << NODE_SUBCLASS_SHIFT) | \
33 (((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
34 (((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
35
36#define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
37#define NODESUBCLASS(ID) (((ID) & NODE_SUBCLASS_MASK) >> \
38 NODE_SUBCLASS_SHIFT)
39#define NODETYPE(ID) (((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT)
40#define NODEINDEX(ID) (((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT)
41
42/*********************************************************************
43 * Enum definitions
44 ********************************************************************/
45
46/* Node class types */
47enum pm_node_class {
48 XPM_NODECLASS_MIN,
49
50 XPM_NODECLASS_POWER,
51 XPM_NODECLASS_CLOCK,
52 XPM_NODECLASS_RESET,
53 XPM_NODECLASS_MEMIC,
54 XPM_NODECLASS_STMIC,
55 XPM_NODECLASS_DEVICE,
56
57 XPM_NODECLASS_MAX
58};
59
60enum pm_device_node_subclass {
61 /* Device types */
62 XPM_NODESUBCL_DEV_CORE = 1,
63 XPM_NODESUBCL_DEV_PERIPH,
64 XPM_NODESUBCL_DEV_MEM,
65 XPM_NODESUBCL_DEV_SOC,
66 XPM_NODESUBCL_DEV_MEM_CTRLR,
67 XPM_NODESUBCL_DEV_PHY,
68};
69
70enum pm_device_node_type {
71 /* Device types */
72 XPM_NODETYPE_DEV_CORE_PMC = 1,
73 XPM_NODETYPE_DEV_CORE_PSM,
74 XPM_NODETYPE_DEV_CORE_APU,
75 XPM_NODETYPE_DEV_CORE_RPU,
76 XPM_NODETYPE_DEV_OCM,
77 XPM_NODETYPE_DEV_TCM,
78 XPM_NODETYPE_DEV_L2CACHE,
79 XPM_NODETYPE_DEV_DDR,
80 XPM_NODETYPE_DEV_PERIPH,
81 XPM_NODETYPE_DEV_SOC,
82 XPM_NODETYPE_DEV_GT,
83};
84
85/* Device node Indexes */
86enum pm_device_node_idx {
87 /* Device nodes */
Jay Buddhabhatti4b4c5e02022-12-22 03:05:59 -080088 XPM_NODEIDX_DEV_MIN = 0x0,
Tejas Patel354fe572018-12-14 00:55:37 -080089
90 /* Processor devices */
Jay Buddhabhatti4b4c5e02022-12-22 03:05:59 -080091 XPM_NODEIDX_DEV_PMC_PROC = 0x1,
92 XPM_NODEIDX_DEV_PSM_PROC = 0x2,
93 XPM_NODEIDX_DEV_ACPU_0 = 0x3,
94 XPM_NODEIDX_DEV_ACPU_1 = 0x4,
95 XPM_NODEIDX_DEV_RPU0_0 = 0x5,
96 XPM_NODEIDX_DEV_RPU0_1 = 0x6,
Tejas Patel354fe572018-12-14 00:55:37 -080097
98 /* Memory devices */
Jay Buddhabhatti4b4c5e02022-12-22 03:05:59 -080099 XPM_NODEIDX_DEV_OCM_0 = 0x7,
100 XPM_NODEIDX_DEV_OCM_1 = 0x8,
101 XPM_NODEIDX_DEV_OCM_2 = 0x9,
102 XPM_NODEIDX_DEV_OCM_3 = 0xA,
103 XPM_NODEIDX_DEV_TCM_0_A = 0xB,
104 XPM_NODEIDX_DEV_TCM_0_B = 0xC,
105 XPM_NODEIDX_DEV_TCM_1_A = 0xD,
106 XPM_NODEIDX_DEV_TCM_1_B = 0xE,
107 XPM_NODEIDX_DEV_L2_BANK_0 = 0xF,
108 XPM_NODEIDX_DEV_DDR_0 = 0x10,
109 XPM_NODEIDX_DEV_DDR_1 = 0x11,
110 XPM_NODEIDX_DEV_DDR_2 = 0x12,
111 XPM_NODEIDX_DEV_DDR_3 = 0x13,
112 XPM_NODEIDX_DEV_DDR_4 = 0x14,
113 XPM_NODEIDX_DEV_DDR_5 = 0x15,
114 XPM_NODEIDX_DEV_DDR_6 = 0x16,
115 XPM_NODEIDX_DEV_DDR_7 = 0x17,
Tejas Patel354fe572018-12-14 00:55:37 -0800116
117 /* LPD Peripheral devices */
Jay Buddhabhatti4b4c5e02022-12-22 03:05:59 -0800118 XPM_NODEIDX_DEV_USB_0 = 0x18,
119 XPM_NODEIDX_DEV_GEM_0 = 0x19,
120 XPM_NODEIDX_DEV_GEM_1 = 0x1A,
121 XPM_NODEIDX_DEV_SPI_0 = 0x1B,
122 XPM_NODEIDX_DEV_SPI_1 = 0x1C,
123 XPM_NODEIDX_DEV_I2C_0 = 0x1D,
124 XPM_NODEIDX_DEV_I2C_1 = 0x1E,
125 XPM_NODEIDX_DEV_CAN_FD_0 = 0x1F,
126 XPM_NODEIDX_DEV_CAN_FD_1 = 0x20,
127 XPM_NODEIDX_DEV_UART_0 = 0x21,
128 XPM_NODEIDX_DEV_UART_1 = 0x22,
129 XPM_NODEIDX_DEV_GPIO = 0x23,
130 XPM_NODEIDX_DEV_TTC_0 = 0x24,
131 XPM_NODEIDX_DEV_TTC_1 = 0x25,
132 XPM_NODEIDX_DEV_TTC_2 = 0x26,
133 XPM_NODEIDX_DEV_TTC_3 = 0x27,
134 XPM_NODEIDX_DEV_SWDT_LPD = 0x28,
Tejas Patel354fe572018-12-14 00:55:37 -0800135
136 /* FPD Peripheral devices */
Jay Buddhabhatti4b4c5e02022-12-22 03:05:59 -0800137 XPM_NODEIDX_DEV_SWDT_FPD = 0x29,
Tejas Patel354fe572018-12-14 00:55:37 -0800138
139 /* PMC Peripheral devices */
Jay Buddhabhatti4b4c5e02022-12-22 03:05:59 -0800140 XPM_NODEIDX_DEV_OSPI = 0x2A,
141 XPM_NODEIDX_DEV_QSPI = 0x2B,
142 XPM_NODEIDX_DEV_GPIO_PMC = 0x2C,
143 XPM_NODEIDX_DEV_I2C_PMC = 0x2D,
144 XPM_NODEIDX_DEV_SDIO_0 = 0x2E,
145 XPM_NODEIDX_DEV_SDIO_1 = 0x2F,
Tejas Patel354fe572018-12-14 00:55:37 -0800146
Jay Buddhabhatti4b4c5e02022-12-22 03:05:59 -0800147 XPM_NODEIDX_DEV_PL_0 = 0x30,
148 XPM_NODEIDX_DEV_PL_1 = 0x31,
149 XPM_NODEIDX_DEV_PL_2 = 0x32,
150 XPM_NODEIDX_DEV_PL_3 = 0x33,
151 XPM_NODEIDX_DEV_RTC = 0x34,
152 XPM_NODEIDX_DEV_ADMA_0 = 0x35,
153 XPM_NODEIDX_DEV_ADMA_1 = 0x36,
154 XPM_NODEIDX_DEV_ADMA_2 = 0x37,
155 XPM_NODEIDX_DEV_ADMA_3 = 0x38,
156 XPM_NODEIDX_DEV_ADMA_4 = 0x39,
157 XPM_NODEIDX_DEV_ADMA_5 = 0x3A,
158 XPM_NODEIDX_DEV_ADMA_6 = 0x3B,
159 XPM_NODEIDX_DEV_ADMA_7 = 0x3C,
160 XPM_NODEIDX_DEV_IPI_0 = 0x3D,
161 XPM_NODEIDX_DEV_IPI_1 = 0x3E,
162 XPM_NODEIDX_DEV_IPI_2 = 0x3F,
163 XPM_NODEIDX_DEV_IPI_3 = 0x40,
164 XPM_NODEIDX_DEV_IPI_4 = 0x41,
165 XPM_NODEIDX_DEV_IPI_5 = 0x42,
166 XPM_NODEIDX_DEV_IPI_6 = 0x43,
Tejas Patel354fe572018-12-14 00:55:37 -0800167
168 /* Entire SoC */
Jay Buddhabhatti4b4c5e02022-12-22 03:05:59 -0800169 XPM_NODEIDX_DEV_SOC = 0x44,
Tejas Patel354fe572018-12-14 00:55:37 -0800170
171 /* DDR memory controllers */
Jay Buddhabhatti4b4c5e02022-12-22 03:05:59 -0800172 XPM_NODEIDX_DEV_DDRMC_0 = 0x45,
173 XPM_NODEIDX_DEV_DDRMC_1 = 0x46,
174 XPM_NODEIDX_DEV_DDRMC_2 = 0x47,
175 XPM_NODEIDX_DEV_DDRMC_3 = 0x48,
Tejas Patel354fe572018-12-14 00:55:37 -0800176
177 /* GT devices */
Jay Buddhabhatti4b4c5e02022-12-22 03:05:59 -0800178 XPM_NODEIDX_DEV_GT_0 = 0x49,
179 XPM_NODEIDX_DEV_GT_1 = 0x4A,
180 XPM_NODEIDX_DEV_GT_2 = 0x4B,
181 XPM_NODEIDX_DEV_GT_3 = 0x4C,
182 XPM_NODEIDX_DEV_GT_4 = 0x4D,
183 XPM_NODEIDX_DEV_GT_5 = 0x4E,
184 XPM_NODEIDX_DEV_GT_6 = 0x4F,
185 XPM_NODEIDX_DEV_GT_7 = 0x50,
186 XPM_NODEIDX_DEV_GT_8 = 0x51,
187 XPM_NODEIDX_DEV_GT_9 = 0x52,
188 XPM_NODEIDX_DEV_GT_10 = 0x53,
Tejas Patel354fe572018-12-14 00:55:37 -0800189
Jay Buddhabhattib0a402a2022-12-22 03:16:14 -0800190#if defined(PLAT_versal_net)
191 XPM_NODEIDX_DEV_ACPU_0_0 = 0x54,
192 XPM_NODEIDX_DEV_ACPU_0_1 = 0x55,
193 XPM_NODEIDX_DEV_ACPU_0_2 = 0x56,
194 XPM_NODEIDX_DEV_ACPU_0_3 = 0x57,
195 XPM_NODEIDX_DEV_ACPU_1_0 = 0x58,
196 XPM_NODEIDX_DEV_ACPU_1_1 = 0x59,
197 XPM_NODEIDX_DEV_ACPU_1_2 = 0x5A,
198 XPM_NODEIDX_DEV_ACPU_1_3 = 0x5B,
199 XPM_NODEIDX_DEV_ACPU_2_0 = 0x5C,
200 XPM_NODEIDX_DEV_ACPU_2_1 = 0x5D,
201 XPM_NODEIDX_DEV_ACPU_2_2 = 0x5E,
202 XPM_NODEIDX_DEV_ACPU_2_3 = 0x5F,
203 XPM_NODEIDX_DEV_ACPU_3_0 = 0x60,
204 XPM_NODEIDX_DEV_ACPU_3_1 = 0x61,
205 XPM_NODEIDX_DEV_ACPU_3_2 = 0x62,
206 XPM_NODEIDX_DEV_ACPU_3_3 = 0x63,
207 XPM_NODEIDX_DEV_RPU_A_0 = 0x64,
208 XPM_NODEIDX_DEV_RPU_A_1 = 0x65,
209 XPM_NODEIDX_DEV_RPU_B_0 = 0x66,
210 XPM_NODEIDX_DEV_RPU_B_1 = 0x67,
211 XPM_NODEIDX_DEV_OCM_0_0 = 0x68,
212 XPM_NODEIDX_DEV_OCM_0_1 = 0x69,
213 XPM_NODEIDX_DEV_OCM_0_2 = 0x6A,
214 XPM_NODEIDX_DEV_OCM_0_3 = 0x6B,
215 XPM_NODEIDX_DEV_OCM_1_0 = 0x6C,
216 XPM_NODEIDX_DEV_OCM_1_1 = 0x6D,
217 XPM_NODEIDX_DEV_OCM_1_2 = 0x6E,
218 XPM_NODEIDX_DEV_OCM_1_3 = 0x6F,
219 XPM_NODEIDX_DEV_TCM_A_0A = 0x70,
220 XPM_NODEIDX_DEV_TCM_A_0B = 0x71,
221 XPM_NODEIDX_DEV_TCM_A_0C = 0x72,
222 XPM_NODEIDX_DEV_TCM_A_1A = 0x73,
223 XPM_NODEIDX_DEV_TCM_A_1B = 0x74,
224 XPM_NODEIDX_DEV_TCM_A_1C = 0x75,
225 XPM_NODEIDX_DEV_TCM_B_0A = 0x76,
226 XPM_NODEIDX_DEV_TCM_B_0B = 0x77,
227 XPM_NODEIDX_DEV_TCM_B_0C = 0x78,
228 XPM_NODEIDX_DEV_TCM_B_1A = 0x79,
229 XPM_NODEIDX_DEV_TCM_B_1B = 0x7A,
230 XPM_NODEIDX_DEV_TCM_B_1C = 0x7B,
231 XPM_NODEIDX_DEV_USB_1 = 0x7C,
232 XPM_NODEIDX_DEV_PMC_WWDT = 0x7D,
233 XPM_NODEIDX_DEV_LPD_SWDT_0 = 0x7E,
234 XPM_NODEIDX_DEV_LPD_SWDT_1 = 0x7F,
235 XPM_NODEIDX_DEV_FPD_SWDT_0 = 0x80,
236 XPM_NODEIDX_DEV_FPD_SWDT_1 = 0x81,
237 XPM_NODEIDX_DEV_FPD_SWDT_2 = 0x82,
238 XPM_NODEIDX_DEV_FPD_SWDT_3 = 0x83,
239#endif
240 XPM_NODEIDX_DEV_MAX,
Tejas Patel354fe572018-12-14 00:55:37 -0800241};
242
243#endif /* PM_NODE_H */