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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Firmware Design
2===============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot
Paul Beesleyf8640672019-04-12 14:19:42 +01005Requirements (TBBR) Platform Design Document (PDD) for Arm reference
6platforms.
7
8The TBB sequence starts when the platform is powered on and runs up
Douglas Raillardd7c21b72017-06-28 15:23:03 +01009to the stage where it hands-off control to firmware running in the normal
10world in DRAM. This is the cold boot path.
11
Manish V Badarkhe9d24e9b2023-06-15 09:14:33 +010012TF-A also implements the `PSCI`_ as a runtime service. PSCI is the interface
13from normal world software to firmware implementing power management use-cases
14(for example, secondary CPU boot, hotplug and idle). Normal world software can
15access TF-A runtime services via the Arm SMC (Secure Monitor Call) instruction.
16The SMC instruction must be used as mandated by the SMC Calling Convention
17(`SMCCC`_).
Douglas Raillardd7c21b72017-06-28 15:23:03 +010018
Dan Handley610e7e12018-03-01 18:44:00 +000019TF-A implements a framework for configuring and managing interrupts generated
20in either security state. The details of the interrupt management framework
Paul Beesleyf8640672019-04-12 14:19:42 +010021and its design can be found in :ref:`Interrupt Management Framework`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022
Dan Handley610e7e12018-03-01 18:44:00 +000023TF-A also implements a library for setting up and managing the translation
Paul Beesleyf8640672019-04-12 14:19:42 +010024tables. The details of this library can be found in
25:ref:`Translation (XLAT) Tables Library`.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010026
Dan Handley610e7e12018-03-01 18:44:00 +000027TF-A can be built to support either AArch64 or AArch32 execution state.
Zelalem Aweke023b1a42021-10-21 13:59:45 -050028
Harrison Mutai3005be02023-05-12 09:45:14 +010029.. note::
30 The descriptions in this chapter are for the Arm TrustZone architecture.
31 For changes to the firmware design for the `Arm Confidential Compute
32 Architecture (Arm CCA)`_ please refer to the chapter :ref:`Realm Management
33 Extension (RME)`.
Zelalem Aweke023b1a42021-10-21 13:59:45 -050034
Douglas Raillardd7c21b72017-06-28 15:23:03 +010035Cold boot
36---------
37
38The cold boot path starts when the platform is physically turned on. If
39``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the
40primary CPU, and the remaining CPUs are considered secondary CPUs. The primary
41CPU is chosen through platform-specific means. The cold boot path is mainly
42executed by the primary CPU, other than essential CPU initialization executed by
43all CPUs. The secondary CPUs are kept in a safe platform-specific state until
44the primary CPU has performed enough initialization to boot them.
45
Paul Beesleyf8640672019-04-12 14:19:42 +010046Refer to the :ref:`CPU Reset` for more information on the effect of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047``COLD_BOOT_SINGLE_CPU`` platform build option.
48
Dan Handley610e7e12018-03-01 18:44:00 +000049The cold boot path in this implementation of TF-A depends on the execution
50state. For AArch64, it is divided into five steps (in order of execution):
Douglas Raillardd7c21b72017-06-28 15:23:03 +010051
52- Boot Loader stage 1 (BL1) *AP Trusted ROM*
53- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
54- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software*
55- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)
56- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
57
58For AArch32, it is divided into four steps (in order of execution):
59
60- Boot Loader stage 1 (BL1) *AP Trusted ROM*
61- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
62- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software*
63- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
64
Dan Handley610e7e12018-03-01 18:44:00 +000065Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010066combination of the following types of memory regions. Each bootloader stage uses
67one or more of these memory regions.
68
69- Regions accessible from both non-secure and secure states. For example,
70 non-trusted SRAM, ROM and DRAM.
71- Regions accessible from only the secure state. For example, trusted SRAM and
72 ROM. The FVPs also implement the trusted DRAM which is statically
73 configured. Additionally, the Base FVPs and Juno development platform
74 configure the TrustZone Controller (TZC) to create a region in the DRAM
75 which is accessible only from the secure state.
76
77The sections below provide the following details:
78
Soby Mathewb1bf0442018-02-16 14:52:52 +000079- dynamic configuration of Boot Loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +010080- initialization and execution of the first three stages during cold boot
81- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for
82 AArch32) entrypoint requirements for use by alternative Trusted Boot
83 Firmware in place of the provided BL1 and BL2
84
Soby Mathewb1bf0442018-02-16 14:52:52 +000085Dynamic Configuration during cold boot
86~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
87
88Each of the Boot Loader stages may be dynamically configured if required by the
89platform. The Boot Loader stage may optionally specify a firmware
90configuration file and/or hardware configuration file as listed below:
91
Manish V Badarkheece96fd2020-06-13 09:42:28 +010092- FW_CONFIG - The firmware configuration file. Holds properties shared across
93 all BLx images.
94 An example is the "dtb-registry" node, which contains the information about
95 the other device tree configurations (load-address, size, image_id).
Soby Mathewb1bf0442018-02-16 14:52:52 +000096- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader
97 stages and also by the Normal World Rich OS.
98- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1
99 and BL2.
100- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31.
101- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS
102 (BL32).
103- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted
104 firmware (BL33).
105
106The Arm development platforms use the Flattened Device Tree format for the
107dynamic configuration files.
108
109Each Boot Loader stage can pass up to 4 arguments via registers to the next
110stage. BL2 passes the list of the next images to execute to the *EL3 Runtime
111Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other
112arguments are platform defined. The Arm development platforms use the following
113convention:
114
115- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This
116 structure contains the memory layout available to BL2.
117- When dynamic configuration files are present, the firmware configuration for
118 the next Boot Loader stage is populated in the first available argument and
119 the generic hardware configuration is passed the next available argument.
120 For example,
121
Manish V Badarkheece96fd2020-06-13 09:42:28 +0100122 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2.
123 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000124 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to
125 BL2. Note, ``arg1`` is already used for meminfo_t.
126 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1``
127 to BL31. Note, ``arg0`` is used to pass the list of executable images.
128 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is
129 passed in ``arg2`` to BL31.
130 - For other BL3x images, if the firmware configuration file is loaded by
131 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded
132 then its address is passed in ``arg1``.
Nishant Sharmae9d8c012023-10-13 11:23:50 +0100133 - In case SPMC_AT_EL3 is enabled, populate the BL32 image base, size and max
134 limit in the entry point information, since there is no platform function
135 to retrieve these in generic code. We choose ``arg2``, ``arg3`` and
136 ``arg4`` since the generic code uses ``arg1`` for stashing the SP manifest
137 size. The SPMC setup uses these arguments to update SP manifest with
138 actual SP's base address and it size.
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +0100139 - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to
140 BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved
141 from FW_CONFIG device tree.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000142
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100143BL1
144~~~
145
146This stage begins execution from the platform's reset vector at EL3. The reset
147address is platform dependent but it is usually located in a Trusted ROM area.
148The BL1 data section is copied to trusted SRAM at runtime.
149
Dan Handley610e7e12018-03-01 18:44:00 +0000150On the Arm development platforms, BL1 code starts execution from the reset
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100151vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied
152to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
153
154The functionality implemented by this stage is as follows.
155
156Determination of boot path
157^^^^^^^^^^^^^^^^^^^^^^^^^^
158
159Whenever a CPU is released from reset, BL1 needs to distinguish between a warm
160boot and a cold boot. This is done using platform-specific mechanisms (see the
Paul Beesleyf8640672019-04-12 14:19:42 +0100161``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case
162of a warm boot, a CPU is expected to continue execution from a separate
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100163entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe
164platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in
Paul Beesleyf8640672019-04-12 14:19:42 +0100165the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot
166path as described in the following sections.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167
168This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the
Paul Beesleyf8640672019-04-12 14:19:42 +0100169:ref:`CPU Reset` for more information on the effect of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100170``PROGRAMMABLE_RESET_ADDRESS`` platform build option.
171
172Architectural initialization
173^^^^^^^^^^^^^^^^^^^^^^^^^^^^
174
175BL1 performs minimal architectural initialization as follows.
176
177- Exception vectors
178
179 BL1 sets up simple exception vectors for both synchronous and asynchronous
180 exceptions. The default behavior upon receiving an exception is to populate
181 a status code in the general purpose register ``X0/R0`` and call the
Paul Beesleyf8640672019-04-12 14:19:42 +0100182 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The
183 status code is one of:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100184
185 For AArch64:
186
187 ::
188
189 0x0 : Synchronous exception from Current EL with SP_EL0
190 0x1 : IRQ exception from Current EL with SP_EL0
191 0x2 : FIQ exception from Current EL with SP_EL0
192 0x3 : System Error exception from Current EL with SP_EL0
193 0x4 : Synchronous exception from Current EL with SP_ELx
194 0x5 : IRQ exception from Current EL with SP_ELx
195 0x6 : FIQ exception from Current EL with SP_ELx
196 0x7 : System Error exception from Current EL with SP_ELx
197 0x8 : Synchronous exception from Lower EL using aarch64
198 0x9 : IRQ exception from Lower EL using aarch64
199 0xa : FIQ exception from Lower EL using aarch64
200 0xb : System Error exception from Lower EL using aarch64
201 0xc : Synchronous exception from Lower EL using aarch32
202 0xd : IRQ exception from Lower EL using aarch32
203 0xe : FIQ exception from Lower EL using aarch32
204 0xf : System Error exception from Lower EL using aarch32
205
206 For AArch32:
207
208 ::
209
210 0x10 : User mode
211 0x11 : FIQ mode
212 0x12 : IRQ mode
213 0x13 : SVC mode
214 0x16 : Monitor mode
215 0x17 : Abort mode
216 0x1a : Hypervisor mode
217 0x1b : Undefined mode
218 0x1f : System mode
219
Dan Handley610e7e12018-03-01 18:44:00 +0000220 The ``plat_report_exception()`` implementation on the Arm FVP port programs
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100221 the Versatile Express System LED register in the following format to
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000222 indicate the occurrence of an unexpected exception:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100223
224 ::
225
226 SYS_LED[0] - Security state (Secure=0/Non-Secure=1)
227 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)
228 For AArch32 it is always 0x0
229 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value
230 of the status code
231
232 A write to the LED register reflects in the System LEDs (S6LED0..7) in the
233 CLCD window of the FVP.
234
235 BL1 does not expect to receive any exceptions other than the SMC exception.
236 For the latter, BL1 installs a simple stub. The stub expects to receive a
237 limited set of SMC types (determined by their function IDs in the general
238 purpose register ``X0/R0``):
239
240 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control
241 to EL3 Runtime Software.
Paul Beesleyf8640672019-04-12 14:19:42 +0100242 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)`
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100243 Design Guide are supported for AArch64 only. These SMCs are currently
244 not supported when BL1 is built for AArch32.
245
246 Any other SMC leads to an assertion failure.
247
248- CPU initialization
249
250 BL1 calls the ``reset_handler()`` function which in turn calls the CPU
251 specific reset handler function (see the section: "CPU specific operations
252 framework").
253
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100254Platform initialization
255^^^^^^^^^^^^^^^^^^^^^^^
256
Dan Handley610e7e12018-03-01 18:44:00 +0000257On Arm platforms, BL1 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100258
259- Enable the Trusted Watchdog.
260- Initialize the console.
261- Configure the Interconnect to enable hardware coherency.
262- Enable the MMU and map the memory it needs to access.
263- Configure any required platform storage to load the next bootloader image
264 (BL2).
Soby Mathewb1bf0442018-02-16 14:52:52 +0000265- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then
266 load it to the platform defined address and make it available to BL2 via
267 ``arg0``.
Soby Mathewd969a7e2018-06-11 16:40:36 +0100268- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U
269 and NS-BL2U firmware update images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100270
271Firmware Update detection and execution
272^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
273
274After performing platform setup, BL1 common code calls
Paul Beesleyf8640672019-04-12 14:19:42 +0100275``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is
276required or to proceed with the normal boot process. If the platform code
277returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described
278in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is
279required and execution passes to the first image in the
280:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor
281of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor
282contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the
283execution state of the next image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100284
285BL2 image load and execution
286^^^^^^^^^^^^^^^^^^^^^^^^^^^^
287
288In the normal boot flow, BL1 execution continues as follows:
289
290#. BL1 prints the following string from the primary CPU to indicate successful
291 execution of the BL1 stage:
292
293 ::
294
295 "Booting Trusted Firmware"
296
Soby Mathewb1bf0442018-02-16 14:52:52 +0000297#. BL1 loads a BL2 raw binary image from platform storage, at a
298 platform-specific base address. Prior to the load, BL1 invokes
299 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or
300 use the image information. If the BL2 image file is not present or if
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100301 there is not enough free trusted SRAM the following error message is
302 printed:
303
304 ::
305
306 "Failed to load BL2 firmware."
307
Soby Mathewb1bf0442018-02-16 14:52:52 +0000308#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended
309 for platforms to take further action after image load. This function must
310 populate the necessary arguments for BL2, which may also include the memory
311 layout. Further description of the memory layout can be found later
312 in this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100313
314#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
315 Secure SVC mode (for AArch32), starting from its load address.
316
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100317BL2
318~~~
319
320BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure
321SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific
322base address (more information can be found later in this document).
323The functionality implemented by BL2 is as follows.
324
325Architectural initialization
326^^^^^^^^^^^^^^^^^^^^^^^^^^^^
327
328For AArch64, BL2 performs the minimal architectural initialization required
Dan Handley610e7e12018-03-01 18:44:00 +0000329for subsequent stages of TF-A and normal world software. EL1 and EL0 are given
Peng Fan9632c9c2020-08-21 10:47:17 +0800330access to Floating Point and Advanced SIMD registers by setting the
Dan Handley610e7e12018-03-01 18:44:00 +0000331``CPACR.FPEN`` bits.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100332
333For AArch32, the minimal architectural initialization required for subsequent
Dan Handley610e7e12018-03-01 18:44:00 +0000334stages of TF-A and normal world software is taken care of in BL1 as both BL1
335and BL2 execute at PL1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100336
337Platform initialization
338^^^^^^^^^^^^^^^^^^^^^^^
339
Dan Handley610e7e12018-03-01 18:44:00 +0000340On Arm platforms, BL2 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100341
342- Initialize the console.
343- Configure any required platform storage to allow loading further bootloader
344 images.
345- Enable the MMU and map the memory it needs to access.
346- Perform platform security setup to allow access to controlled components.
347- Reserve some memory for passing information to the next bootloader image
348 EL3 Runtime Software and populate it.
349- Define the extents of memory available for loading each subsequent
350 bootloader image.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000351- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``,
352 then parse it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353
354Image loading in BL2
355^^^^^^^^^^^^^^^^^^^^
356
Roberto Vargas025946a2018-09-24 17:20:48 +0100357BL2 generic code loads the images based on the list of loadable images
358provided by the platform. BL2 passes the list of executable images
359provided by the platform to the next handover BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100360
Soby Mathewb1bf0442018-02-16 14:52:52 +0000361The list of loadable images provided by the platform may also contain
362dynamic configuration files. The files are loaded and can be parsed as
363needed in the ``bl2_plat_handle_post_image_load()`` function. These
364configuration files can be passed to next Boot Loader stages as arguments
365by updating the corresponding entrypoint information in this function.
366
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100367SCP_BL2 (System Control Processor Firmware) image load
368^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100369
370Some systems have a separate System Control Processor (SCP) for power, clock,
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100371reset and system control. BL2 loads the optional SCP_BL2 image from platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100372storage into a platform-specific region of secure memory. The subsequent
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100373handling of SCP_BL2 is platform specific. For example, on the Juno Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100374development platform port the image is transferred into SCP's internal memory
375using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100376memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100377for BL2 execution to continue.
378
379EL3 Runtime Software image load
380^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
381
382BL2 loads the EL3 Runtime Software image from platform storage into a platform-
383specific address in trusted SRAM. If there is not enough memory to load the
Roberto Vargas025946a2018-09-24 17:20:48 +0100384image or image is missing it leads to an assertion failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100385
386AArch64 BL32 (Secure-EL1 Payload) image load
387^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
388
389BL2 loads the optional BL32 image from platform storage into a platform-
390specific region of secure memory. The image executes in the secure world. BL2
391relies on BL31 to pass control to the BL32 image, if present. Hence, BL2
392populates a platform-specific area of memory with the entrypoint/load-address
393of the BL32 image. The value of the Saved Processor Status Register (``SPSR``)
394for entry into BL32 is not determined by BL2, it is initialized by the
395Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for
396managing interaction with BL32. This information is passed to BL31.
397
398BL33 (Non-trusted Firmware) image load
399^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
400
401BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from
402platform storage into non-secure memory as defined by the platform.
403
404BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state
405initialization is complete. Hence, BL2 populates a platform-specific area of
406memory with the entrypoint and Saved Program Status Register (``SPSR``) of the
407normal world software image. The entrypoint is the load address of the BL33
408image. The ``SPSR`` is determined as specified in Section 5.13 of the
Manish V Badarkhe9d24e9b2023-06-15 09:14:33 +0100409`PSCI`_. This information is passed to the EL3 Runtime Software.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100410
411AArch64 BL31 (EL3 Runtime Software) execution
412^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
413
414BL2 execution continues as follows:
415
416#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
417 BL31 entrypoint. The exception is handled by the SMC exception handler
418 installed by BL1.
419
420#. BL1 turns off the MMU and flushes the caches. It clears the
421 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency
422 and invalidates the TLBs.
423
424#. BL1 passes control to BL31 at the specified entrypoint at EL3.
425
Roberto Vargasb1584272017-11-20 13:36:10 +0000426Running BL2 at EL3 execution level
427~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
428
Dan Handley610e7e12018-03-01 18:44:00 +0000429Some platforms have a non-TF-A Boot ROM that expects the next boot stage
430to execute at EL3. On these platforms, TF-A BL1 is a waste of memory
431as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid
Roberto Vargasb1584272017-11-20 13:36:10 +0000432this waste, a special mode enables BL2 to execute at EL3, which allows
Dan Handley610e7e12018-03-01 18:44:00 +0000433a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600434when the build flag RESET_TO_BL2 is enabled.
435The main differences in this mode are:
Roberto Vargasb1584272017-11-20 13:36:10 +0000436
437#. BL2 includes the reset code and the mailbox mechanism to differentiate
438 cold boot and warm boot. It runs at EL3 doing the arch
439 initialization required for EL3.
440
441#. BL2 does not receive the meminfo information from BL1 anymore. This
442 information can be passed by the Boot ROM or be internal to the
443 BL2 image.
444
445#. Since BL2 executes at EL3, BL2 jumps directly to the next image,
446 instead of invoking the RUN_IMAGE SMC call.
447
448
449We assume 3 different types of BootROM support on the platform:
450
451#. The Boot ROM always jumps to the same address, for both cold
452 and warm boot. In this case, we will need to keep a resident part
453 of BL2 whose memory cannot be reclaimed by any other image. The
454 linker script defines the symbols __TEXT_RESIDENT_START__ and
455 __TEXT_RESIDENT_END__ that allows the platform to configure
456 correctly the memory map.
457#. The platform has some mechanism to indicate the jump address to the
458 Boot ROM. Platform code can then program the jump address with
459 psci_warmboot_entrypoint during cold boot.
460#. The platform has some mechanism to program the reset address using
461 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then
462 program the reset address with psci_warmboot_entrypoint during
463 cold boot, bypassing the boot ROM for warm boot.
464
465In the last 2 cases, no part of BL2 needs to remain resident at
466runtime. In the first 2 cases, we expect the Boot ROM to be able to
467differentiate between warm and cold boot, to avoid loading BL2 again
468during warm boot.
469
470This functionality can be tested with FVP loading the image directly
471in memory and changing the address where the system jumps at reset.
472For example:
473
Dimitris Papastamos25836492018-06-11 11:07:58 +0100474 -C cluster0.cpu0.RVBAR=0x4022000
475 --data cluster0.cpu0=bl2.bin@0x4022000
Roberto Vargasb1584272017-11-20 13:36:10 +0000476
477With this configuration, FVP is like a platform of the first case,
478where the Boot ROM jumps always to the same address. For simplification,
479BL32 is loaded in DRAM in this case, to avoid other images reclaiming
480BL2 memory.
481
482
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100483AArch64 BL31
484~~~~~~~~~~~~
485
486The image for this stage is loaded by BL2 and BL1 passes control to BL31 at
487EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and
488loaded at a platform-specific base address (more information can be found later
489in this document). The functionality implemented by BL31 is as follows.
490
491Architectural initialization
492^^^^^^^^^^^^^^^^^^^^^^^^^^^^
493
494Currently, BL31 performs a similar architectural initialization to BL1 as
495far as system register settings are concerned. Since BL1 code resides in ROM,
496architectural initialization in BL31 allows override of any previous
497initialization done by BL1.
498
499BL31 initializes the per-CPU data framework, which provides a cache of
500frequently accessed per-CPU data optimised for fast, concurrent manipulation
501on different CPUs. This buffer includes pointers to per-CPU contexts, crash
502buffer, CPU reset and power down operations, PSCI data, platform data and so on.
503
504It then replaces the exception vectors populated by BL1 with its own. BL31
505exception vectors implement more elaborate support for handling SMCs since this
506is the only mechanism to access the runtime services implemented by BL31 (PSCI
507for example). BL31 checks each SMC for validity as specified by the
Sandrine Bailleuxd9202df2020-04-17 14:06:52 +0200508`SMC Calling Convention`_ before passing control to the required SMC
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100509handler routine.
510
511BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system
512counter, which is provided by the platform.
513
514Platform initialization
515^^^^^^^^^^^^^^^^^^^^^^^
516
517BL31 performs detailed platform initialization, which enables normal world
518software to function correctly.
519
Dan Handley610e7e12018-03-01 18:44:00 +0000520On Arm platforms, this consists of the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100521
522- Initialize the console.
523- Configure the Interconnect to enable hardware coherency.
524- Enable the MMU and map the memory it needs to access.
525- Initialize the generic interrupt controller.
526- Initialize the power controller device.
527- Detect the system topology.
528
529Runtime services initialization
530^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
531
532BL31 is responsible for initializing the runtime services. One of them is PSCI.
533
534As part of the PSCI initializations, BL31 detects the system topology. It also
535initializes the data structures that implement the state machine used to track
536the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or
537``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster
538that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also
539initializes the locks that protect them. BL31 accesses the state of a CPU or
540cluster immediately after reset and before the data cache is enabled in the
541warm boot path. It is not currently possible to use 'exclusive' based spinlocks,
542therefore BL31 uses locks based on Lamport's Bakery algorithm instead.
543
544The runtime service framework and its initialization is described in more
545detail in the "EL3 runtime services framework" section below.
546
547Details about the status of the PSCI implementation are provided in the
548"Power State Coordination Interface" section below.
549
550AArch64 BL32 (Secure-EL1 Payload) image initialization
551^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
552
553If a BL32 image is present then there must be a matching Secure-EL1 Payload
554Dispatcher (SPD) service (see later for details). During initialization
555that service must register a function to carry out initialization of BL32
556once the runtime services are fully initialized. BL31 invokes such a
557registered function to initialize BL32 before running BL33. This initialization
558is not necessary for AArch32 SPs.
559
560Details on BL32 initialization and the SPD's role are described in the
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100561:ref:`firmware_design_sel1_spd` section below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100562
563BL33 (Non-trusted Firmware) execution
564^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
565
566EL3 Runtime Software initializes the EL2 or EL1 processor context for normal-
567world cold boot, ensuring that no secure state information finds its way into
568the non-secure execution state. EL3 Runtime Software uses the entrypoint
569information provided by BL2 to jump to the Non-trusted firmware image (BL33)
570at the highest available Exception Level (EL2 if available, otherwise EL1).
571
572Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only)
573~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
574
575Some platforms have existing implementations of Trusted Boot Firmware that
Dan Handley610e7e12018-03-01 18:44:00 +0000576would like to use TF-A BL31 for the EL3 Runtime Software. To enable this
577firmware architecture it is important to provide a fully documented and stable
578interface between the Trusted Boot Firmware and BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100579
580Future changes to the BL31 interface will be done in a backwards compatible
581way, and this enables these firmware components to be independently enhanced/
582updated to develop and exploit new functionality.
583
584Required CPU state when calling ``bl31_entrypoint()`` during cold boot
585^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
586
587This function must only be called by the primary CPU.
588
589On entry to this function the calling primary CPU must be executing in AArch64
590EL3, little-endian data access, and all interrupt sources masked:
591
592::
593
594 PSTATE.EL = 3
595 PSTATE.RW = 1
596 PSTATE.DAIF = 0xf
597 SCTLR_EL3.EE = 0
598
599X0 and X1 can be used to pass information from the Trusted Boot Firmware to the
600platform code in BL31:
601
602::
603
Dan Handley610e7e12018-03-01 18:44:00 +0000604 X0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100605 X1 : Platform specific information
606
607BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry,
608these will be zero filled prior to invoking platform setup code.
609
610Use of the X0 and X1 parameters
611'''''''''''''''''''''''''''''''
612
613The parameters are platform specific and passed from ``bl31_entrypoint()`` to
614``bl31_early_platform_setup()``. The value of these parameters is never directly
615used by the common BL31 code.
616
617The convention is that ``X0`` conveys information regarding the BL31, BL32 and
618BL33 images from the Trusted Boot firmware and ``X1`` can be used for other
Dan Handley610e7e12018-03-01 18:44:00 +0000619platform specific purpose. This convention allows platforms which use TF-A's
620BL1 and BL2 images to transfer additional platform specific information from
621Secure Boot without conflicting with future evolution of TF-A using ``X0`` to
622pass a ``bl31_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100623
624BL31 common and SPD initialization code depends on image and entrypoint
625information about BL33 and BL32, which is provided via BL31 platform APIs.
626This information is required until the start of execution of BL33. This
627information can be provided in a platform defined manner, e.g. compiled into
628the platform code in BL31, or provided in a platform defined memory location
629by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the
630Cold boot Initialization parameters. This data may need to be cleaned out of
631the CPU caches if it is provided by an earlier boot stage and then accessed by
632BL31 platform code before the caches are enabled.
633
Dan Handley610e7e12018-03-01 18:44:00 +0000634TF-A's BL2 implementation passes a ``bl31_params`` structure in
635``X0`` and the Arm development platforms interpret this in the BL31 platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100636code.
637
638MMU, Data caches & Coherency
639''''''''''''''''''''''''''''
640
641BL31 does not depend on the enabled state of the MMU, data caches or
642interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled
643on entry, these should be enabled during ``bl31_plat_arch_setup()``.
644
645Data structures used in the BL31 cold boot interface
646''''''''''''''''''''''''''''''''''''''''''''''''''''
647
648These structures are designed to support compatibility and independent
649evolution of the structures and the firmware images. For example, a version of
650BL31 that can interpret the BL3x image information from different versions of
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100651BL2, a platform that uses an extended entry_point_info structure to convey
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100652additional register information to BL31, or a ELF image loader that can convey
653more details about the firmware images.
654
655To support these scenarios the structures are versioned and sized, which enables
656BL31 to detect which information is present and respond appropriately. The
657``param_header`` is defined to capture this information:
658
659.. code:: c
660
661 typedef struct param_header {
662 uint8_t type; /* type of the structure */
663 uint8_t version; /* version of this structure */
664 uint16_t size; /* size of this structure in bytes */
665 uint32_t attr; /* attributes: unused bits SBZ */
666 } param_header_t;
667
668The structures using this format are ``entry_point_info``, ``image_info`` and
669``bl31_params``. The code that allocates and populates these structures must set
670the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined
671to simplify this action.
672
673Required CPU state for BL31 Warm boot initialization
674^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
675
Dan Handley610e7e12018-03-01 18:44:00 +0000676When requesting a CPU power-on, or suspending a running CPU, TF-A provides
677the platform power management code with a Warm boot initialization
678entry-point, to be invoked by the CPU immediately after the reset handler.
679On entry to the Warm boot initialization function the calling CPU must be in
680AArch64 EL3, little-endian data access and all interrupt sources masked:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100681
682::
683
684 PSTATE.EL = 3
685 PSTATE.RW = 1
686 PSTATE.DAIF = 0xf
687 SCTLR_EL3.EE = 0
688
689The PSCI implementation will initialize the processor state and ensure that the
690platform power management code is then invoked as required to initialize all
691necessary system, cluster and CPU resources.
692
693AArch32 EL3 Runtime Software entrypoint interface
694~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
695
696To enable this firmware architecture it is important to provide a fully
697documented and stable interface between the Trusted Boot Firmware and the
698AArch32 EL3 Runtime Software.
699
700Future changes to the entrypoint interface will be done in a backwards
701compatible way, and this enables these firmware components to be independently
702enhanced/updated to develop and exploit new functionality.
703
704Required CPU state when entering during cold boot
705^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
706
707This function must only be called by the primary CPU.
708
709On entry to this function the calling primary CPU must be executing in AArch32
710EL3, little-endian data access, and all interrupt sources masked:
711
712::
713
714 PSTATE.AIF = 0x7
715 SCTLR.EE = 0
716
717R0 and R1 are used to pass information from the Trusted Boot Firmware to the
718platform code in AArch32 EL3 Runtime Software:
719
720::
721
Dan Handley610e7e12018-03-01 18:44:00 +0000722 R0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100723 R1 : Platform specific information
724
725Use of the R0 and R1 parameters
726'''''''''''''''''''''''''''''''
727
728The parameters are platform specific and the convention is that ``R0`` conveys
729information regarding the BL3x images from the Trusted Boot firmware and ``R1``
730can be used for other platform specific purpose. This convention allows
Dan Handley610e7e12018-03-01 18:44:00 +0000731platforms which use TF-A's BL1 and BL2 images to transfer additional platform
732specific information from Secure Boot without conflicting with future
733evolution of TF-A using ``R0`` to pass a ``bl_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100734
735The AArch32 EL3 Runtime Software is responsible for entry into BL33. This
736information can be obtained in a platform defined manner, e.g. compiled into
737the AArch32 EL3 Runtime Software, or provided in a platform defined memory
738location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware
739via the Cold boot Initialization parameters. This data may need to be cleaned
740out of the CPU caches if it is provided by an earlier boot stage and then
741accessed by AArch32 EL3 Runtime Software before the caches are enabled.
742
Dan Handley610e7e12018-03-01 18:44:00 +0000743When using AArch32 EL3 Runtime Software, the Arm development platforms pass a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100744``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime
745Software platform code.
746
747MMU, Data caches & Coherency
748''''''''''''''''''''''''''''
749
750AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU,
751data caches or interconnect coherency in its entrypoint. They must be explicitly
752enabled if required.
753
754Data structures used in cold boot interface
755'''''''''''''''''''''''''''''''''''''''''''
756
757The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead
758of ``bl31_params``. The ``bl_params`` structure is based on the convention
759described in AArch64 BL31 cold boot interface section.
760
761Required CPU state for warm boot initialization
762^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
763
764When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3
765Runtime Software must ensure execution of a warm boot initialization entrypoint.
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100766If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false,
Dan Handley610e7e12018-03-01 18:44:00 +0000767then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm
768boot entrypoint by arranging for the BL1 platform function,
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100769plat_get_my_entrypoint(), to return a non-zero value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100770
771In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian
772data access and all interrupt sources masked:
773
774::
775
776 PSTATE.AIF = 0x7
777 SCTLR.EE = 0
778
Dan Handley610e7e12018-03-01 18:44:00 +0000779The warm boot entrypoint may be implemented by using TF-A
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100780``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil
Paul Beesleyf8640672019-04-12 14:19:42 +0100781the pre-requisites mentioned in the
782:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100783
784EL3 runtime services framework
785------------------------------
786
787Software executing in the non-secure state and in the secure state at exception
788levels lower than EL3 will request runtime services using the Secure Monitor
789Call (SMC) instruction. These requests will follow the convention described in
790the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
791identifiers to each SMC request and describes how arguments are passed and
792returned.
793
794The EL3 runtime services framework enables the development of services by
795different providers that can be easily integrated into final product firmware.
796The following sections describe the framework which facilitates the
797registration, initialization and use of runtime services in EL3 Runtime
798Software (BL31).
799
800The design of the runtime services depends heavily on the concepts and
801definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning
802Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling
803conventions. Please refer to that document for more detailed explanation of
804these terms.
805
806The following runtime services are expected to be implemented first. They have
807not all been instantiated in the current implementation.
808
809#. Standard service calls
810
811 This service is for management of the entire system. The Power State
812 Coordination Interface (`PSCI`_) is the first set of standard service calls
Dan Handley610e7e12018-03-01 18:44:00 +0000813 defined by Arm (see PSCI section later).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100814
815#. Secure-EL1 Payload Dispatcher service
816
817 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then
818 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor
819 context between the normal world (EL1/EL2) and trusted world (Secure-EL1).
820 The Secure Monitor will make these world switches in response to SMCs. The
821 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted
822 Application Call OEN ranges.
823
824 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is
825 not defined by the `SMCCC`_ or any other standard. As a result, each
826 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000827 service - within TF-A this service is referred to as the Secure-EL1 Payload
828 Dispatcher (SPD).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100829
Dan Handley610e7e12018-03-01 18:44:00 +0000830 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher
831 (TSPD). Details of SPD design and TSP/TSPD operation are described in the
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100832 :ref:`firmware_design_sel1_spd` section below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100833
834#. CPU implementation service
835
836 This service will provide an interface to CPU implementation specific
837 services for a given platform e.g. access to processor errata workarounds.
838 This service is currently unimplemented.
839
Dan Handley610e7e12018-03-01 18:44:00 +0000840Additional services for Arm Architecture, SiP and OEM calls can be implemented.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100841Each implemented service handles a range of SMC function identifiers as
842described in the `SMCCC`_.
843
844Registration
845~~~~~~~~~~~~
846
847A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
848the name of the service, the range of OENs covered, the type of service and
849initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``).
Chris Kay33bfc5e2023-02-14 11:30:04 +0000850This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100851the framework to find all service descriptors included into BL31.
852
853The specific service for a SMC Function is selected based on the OEN and call
854type of the Function ID, and the framework uses that information in the service
855descriptor to identify the handler for the SMC Call.
856
857The service descriptors do not include information to identify the precise set
858of SMC function identifiers supported by this service implementation, the
859security state from which such calls are valid nor the capability to support
86064-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately
861to these aspects of a SMC call is the responsibility of the service
862implementation, the framework is focused on integration of services from
863different providers and minimizing the time taken by the framework before the
864service handler is invoked.
865
866Details of the parameters, requirements and behavior of the initialization and
867call handling functions are provided in the following sections.
868
869Initialization
870~~~~~~~~~~~~~~
871
872``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services
873framework running on the primary CPU during cold boot as part of the BL31
874initialization. This happens prior to initializing a Trusted OS and running
875Normal world boot firmware that might in turn use these services.
876Initialization involves validating each of the declared runtime service
877descriptors, calling the service initialization function and populating the
878index used for runtime lookup of the service.
879
880The BL31 linker script collects all of the declared service descriptors into a
881single array and defines symbols that allow the framework to locate and traverse
882the array, and determine its size.
883
884The framework does basic validation of each descriptor to halt firmware
885initialization if service declaration errors are detected. The framework does
886not check descriptors for the following error conditions, and may behave in an
887unpredictable manner under such scenarios:
888
889#. Overlapping OEN ranges
890#. Multiple descriptors for the same range of OENs and ``call_type``
891#. Incorrect range of owning entity numbers for a given ``call_type``
892
893Once validated, the service ``init()`` callback is invoked. This function carries
894out any essential EL3 initialization before servicing requests. The ``init()``
895function is only invoked on the primary CPU during cold boot. If the service
896uses per-CPU data this must either be initialized for all CPUs during this call,
897or be done lazily when a CPU first issues an SMC call to that service. If
898``init()`` returns anything other than ``0``, this is treated as an initialization
899error and the service is ignored: this does not cause the firmware to halt.
900
901The OEN and call type fields present in the SMC Function ID cover a total of
902128 distinct services, but in practice a single descriptor can cover a range of
903OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a
904service handler, the framework uses an array of 128 indices that map every
905distinct OEN/call-type combination either to one of the declared services or to
906indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is
907populated for all of the OENs covered by a service after the service ``init()``
908function has reported success. So a service that fails to initialize will never
909have it's ``handle()`` function invoked.
910
911The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC
912Function ID call type and OEN onto a specific service handler in the
913``rt_svc_descs[]`` array.
914
915|Image 1|
916
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -0500917.. _handling-an-smc:
918
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100919Handling an SMC
920~~~~~~~~~~~~~~~
921
922When the EL3 runtime services framework receives a Secure Monitor Call, the SMC
923Function ID is passed in W0 from the lower exception level (as per the
924`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an
925SMC Function which indicates the SMC64 calling convention: such calls are
926ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF``
927in R0/X0.
928
929Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC
930Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The
931resulting value might indicate a service that has no handler, in this case the
932framework will also report an Unknown SMC Function ID. Otherwise, the value is
933used as a further index into the ``rt_svc_descs[]`` array to locate the required
934service and handler.
935
936The service's ``handle()`` callback is provided with five of the SMC parameters
937directly, the others are saved into memory for retrieval (if needed) by the
938handler. The handler is also provided with an opaque ``handle`` for use with the
939supporting library for parameter retrieval, setting return values and context
Olivier Deprez33dd8452022-10-11 15:38:27 +0200940manipulation. The ``flags`` parameter indicates the security state of the caller
941and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets
942up the execution stack for the handler, and invokes the services ``handle()``
943function.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100944
Madhukar Pappireddy20be0772019-11-09 23:28:08 -0600945On return from the handler the result registers are populated in X0-X7 as needed
946before restoring the stack and CPU state and returning from the original SMC.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100947
Jeenu Viswambharancbb40d52017-10-18 14:30:53 +0100948Exception Handling Framework
949----------------------------
950
johpow017402f072020-07-28 13:07:25 -0500951Please refer to the :ref:`Exception Handling Framework` document.
Jeenu Viswambharancbb40d52017-10-18 14:30:53 +0100952
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100953Power State Coordination Interface
954----------------------------------
955
956TODO: Provide design walkthrough of PSCI implementation.
957
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100958The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the
959mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification
Manish V Badarkhe9d24e9b2023-06-15 09:14:33 +0100960`PSCI`_ are implemented. The table lists the PSCI v1.1 APIs and their support
961in generic code.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100962
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100963An API implementation might have a dependency on platform code e.g. CPU_SUSPEND
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100964requires the platform to export a part of the implementation. Hence the level
965of support of the mandatory APIs depends upon the support exported by the
966platform port as well. The Juno and FVP (all variants) platforms export all the
967required support.
968
969+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100970| PSCI v1.1 API | Supported | Comments |
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100971+=============================+=============+===============================+
Roberto Vargasd963e3e2017-09-12 10:28:35 +0100972| ``PSCI_VERSION`` | Yes | The version returned is 1.1 |
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100973+-----------------------------+-------------+-------------------------------+
974| ``CPU_SUSPEND`` | Yes\* | |
975+-----------------------------+-------------+-------------------------------+
976| ``CPU_OFF`` | Yes\* | |
977+-----------------------------+-------------+-------------------------------+
978| ``CPU_ON`` | Yes\* | |
979+-----------------------------+-------------+-------------------------------+
980| ``AFFINITY_INFO`` | Yes | |
981+-----------------------------+-------------+-------------------------------+
982| ``MIGRATE`` | Yes\*\* | |
983+-----------------------------+-------------+-------------------------------+
984| ``MIGRATE_INFO_TYPE`` | Yes\*\* | |
985+-----------------------------+-------------+-------------------------------+
986| ``MIGRATE_INFO_CPU`` | Yes\*\* | |
987+-----------------------------+-------------+-------------------------------+
988| ``SYSTEM_OFF`` | Yes\* | |
989+-----------------------------+-------------+-------------------------------+
990| ``SYSTEM_RESET`` | Yes\* | |
991+-----------------------------+-------------+-------------------------------+
992| ``PSCI_FEATURES`` | Yes | |
993+-----------------------------+-------------+-------------------------------+
994| ``CPU_FREEZE`` | No | |
995+-----------------------------+-------------+-------------------------------+
996| ``CPU_DEFAULT_SUSPEND`` | No | |
997+-----------------------------+-------------+-------------------------------+
998| ``NODE_HW_STATE`` | Yes\* | |
999+-----------------------------+-------------+-------------------------------+
1000| ``SYSTEM_SUSPEND`` | Yes\* | |
1001+-----------------------------+-------------+-------------------------------+
1002| ``PSCI_SET_SUSPEND_MODE`` | No | |
1003+-----------------------------+-------------+-------------------------------+
1004| ``PSCI_STAT_RESIDENCY`` | Yes\* | |
1005+-----------------------------+-------------+-------------------------------+
1006| ``PSCI_STAT_COUNT`` | Yes\* | |
1007+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001008| ``SYSTEM_RESET2`` | Yes\* | |
1009+-----------------------------+-------------+-------------------------------+
1010| ``MEM_PROTECT`` | Yes\* | |
1011+-----------------------------+-------------+-------------------------------+
1012| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | |
1013+-----------------------------+-------------+-------------------------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001014
1015\*Note : These PSCI APIs require platform power management hooks to be
1016registered with the generic PSCI code to be supported.
1017
1018\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher
1019hooks to be registered with the generic PSCI code to be supported.
1020
Dan Handley610e7e12018-03-01 18:44:00 +00001021The PSCI implementation in TF-A is a library which can be integrated with
1022AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to
1023integrating PSCI library with AArch32 EL3 Runtime Software can be found
Paul Beesleyf8640672019-04-12 14:19:42 +01001024at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
1025
1026.. _firmware_design_sel1_spd:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001027
1028Secure-EL1 Payloads and Dispatchers
1029-----------------------------------
1030
1031On a production system that includes a Trusted OS running in Secure-EL1/EL0,
1032the Trusted OS is coupled with a companion runtime service in the BL31
1033firmware. This service is responsible for the initialisation of the Trusted
1034OS and all communications with it. The Trusted OS is the BL32 stage of the
Dan Handley610e7e12018-03-01 18:44:00 +00001035boot flow in TF-A. The firmware will attempt to locate, load and execute a
1036BL32 image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001037
Dan Handley610e7e12018-03-01 18:44:00 +00001038TF-A uses a more general term for the BL32 software that runs at Secure-EL1 -
1039the *Secure-EL1 Payload* - as it is not always a Trusted OS.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001040
Dan Handley610e7e12018-03-01 18:44:00 +00001041TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload
1042Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a
1043production system using the Runtime Services Framework. On such a system, the
1044Test BL32 image and service are replaced by the Trusted OS and its dispatcher
1045service. The TF-A build system expects that the dispatcher will define the
1046build flag ``NEED_BL32`` to enable it to include the BL32 in the build either
1047as a binary or to compile from source depending on whether the ``BL32`` build
1048option is specified or not.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001049
1050The TSP runs in Secure-EL1. It is designed to demonstrate synchronous
1051communication with the normal-world software running in EL1/EL2. Communication
1052is initiated by the normal-world software
1053
1054- either directly through a Fast SMC (as defined in the `SMCCC`_)
1055
1056- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn
1057 informs the TSPD about the requested power management operation. This allows
1058 the TSP to prepare for or respond to the power state change
1059
1060The TSPD service is responsible for.
1061
1062- Initializing the TSP
1063
1064- Routing requests and responses between the secure and the non-secure
1065 states during the two types of communications just described
1066
1067Initializing a BL32 Image
1068~~~~~~~~~~~~~~~~~~~~~~~~~
1069
1070The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing
1071the BL32 image. It needs access to the information passed by BL2 to BL31 to do
1072so. This is provided by:
1073
1074.. code:: c
1075
1076 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t);
1077
1078which returns a reference to the ``entry_point_info`` structure corresponding to
1079the image which will be run in the specified security state. The SPD uses this
1080API to get entry point information for the SECURE image, BL32.
1081
1082In the absence of a BL32 image, BL31 passes control to the normal world
1083bootloader image (BL33). When the BL32 image is present, it is typical
1084that the SPD wants control to be passed to BL32 first and then later to BL33.
1085
1086To do this the SPD has to register a BL32 initialization function during
1087initialization of the SPD service. The BL32 initialization function has this
1088prototype:
1089
1090.. code:: c
1091
1092 int32_t init(void);
1093
1094and is registered using the ``bl31_register_bl32_init()`` function.
1095
Dan Handley610e7e12018-03-01 18:44:00 +00001096TF-A supports two approaches for the SPD to pass control to BL32 before
1097returning through EL3 and running the non-trusted firmware (BL33):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001098
1099#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to
1100 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in
1101 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by
1102 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``.
1103
1104 When the BL32 has completed initialization at Secure-EL1, it returns to
1105 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On
1106 receipt of this SMC, the SPD service handler should switch the CPU context
1107 from trusted to normal world and use the ``bl31_set_next_image_type()`` and
1108 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to
1109 the normal world firmware BL33. On return from the handler the framework
1110 will exit to EL2 and run BL33.
1111
1112#. The BL32 setup function registers an initialization function using
1113 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to
1114 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32
1115 entrypoint.
Paul Beesleyba3ed402019-03-13 16:20:44 +00001116
1117 .. note::
1118 The Test SPD service included with TF-A provides one implementation
1119 of such a mechanism.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001120
1121 On completion BL32 returns control to BL31 via a SMC, and on receipt the
1122 SPD service handler invokes the synchronous call return mechanism to return
1123 to the BL32 initialization function. On return from this function,
1124 ``bl31_main()`` will set up the return to the normal world firmware BL33 and
1125 continue the boot process in the normal world.
1126
Manish Pandey493bdc42023-07-21 13:08:53 +01001127Exception handling in BL31
1128--------------------------
1129
1130When exception occurs, PE must execute handler corresponding to exception. The
1131location in memory where the handler is stored is called the exception vector.
1132For ARM architecture, exception vectors are stored in a table, called the exception
1133vector table.
1134
1135Each EL (except EL0) has its own vector table, VBAR_ELn register stores the base
1136of vector table. Refer to `AArch64 exception vector table`_
1137
1138Current EL with SP_EL0
1139~~~~~~~~~~~~~~~~~~~~~~
1140
1141- Sync exception : Not expected except for BRK instruction, its debugging tool which
1142 a programmer may place at specific points in a program, to check the state of
1143 processor flags at these points in the code.
1144
1145- IRQ/FIQ : Unexpected exception, panic
1146
1147- SError : "plat_handle_el3_ea", defaults to panic
1148
1149Current EL with SP_ELx
1150~~~~~~~~~~~~~~~~~~~~~~
1151
1152- Sync exception : Unexpected exception, panic
1153
1154- IRQ/FIQ : Unexpected exception, panic
1155
1156- SError : "plat_handle_el3_ea" Except for special handling of lower EL's SError exception
1157 which gets triggered in EL3 when PSTATE.A is unmasked. Its only applicable when lower
1158 EL's EA is routed to EL3 (FFH_SUPPORT=1).
1159
1160Lower EL Exceptions
1161~~~~~~~~~~~~~~~~~~~
1162
1163Applies to all the exceptions in both AArch64/AArch32 mode of lower EL.
1164
1165Before handling any lower EL exception, we synchronize the errors at EL3 entry to ensure
1166that any errors pertaining to lower EL is isolated/identified. If we continue without
1167identifying these errors early on then these errors will trigger in EL3 (as SError from
1168current EL) any time after PSTATE.A is unmasked. This is wrong because the error originated
1169in lower EL but exception happened in EL3.
1170
1171To solve this problem, synchronize the errors at EL3 entry and check for any pending
1172errors (async EA). If there is no pending error then continue with original exception.
1173If there is a pending error then, handle them based on routing model of EA's. Refer to
1174:ref:`Reliability, Availability, and Serviceability (RAS) Extensions` for details about
1175routing models.
1176
1177- KFH : Reflect it back to lower EL using **reflect_pending_async_ea_to_lower_el()**
1178
1179- FFH : Handle the synchronized error first using **handle_pending_async_ea()** after
1180 that continue with original exception. It is the only scenario where EL3 is capable
1181 of doing nested exception handling.
1182
1183After synchronizing and handling lower EL SErrors, unmask EA (PSTATE.A) to ensure
1184that any further EA's caused by EL3 are caught.
1185
Jeenu Viswambharanb60420a2017-08-24 15:43:44 +01001186Crash Reporting in BL31
1187-----------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001188
1189BL31 implements a scheme for reporting the processor state when an unhandled
1190exception is encountered. The reporting mechanism attempts to preserve all the
1191register contents and report it via a dedicated UART (PL011 console). BL31
1192reports the general purpose, EL3, Secure EL1 and some EL2 state registers.
1193
1194A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via
1195the per-CPU pointer cache. The implementation attempts to minimise the memory
1196required for this feature. The file ``crash_reporting.S`` contains the
1197implementation for crash reporting.
1198
1199The sample crash output is shown below.
1200
1201::
1202
Alexei Fedorov813c9f92020-03-03 13:31:58 +00001203 x0 = 0x000000002a4a0000
1204 x1 = 0x0000000000000001
1205 x2 = 0x0000000000000002
1206 x3 = 0x0000000000000003
1207 x4 = 0x0000000000000004
1208 x5 = 0x0000000000000005
1209 x6 = 0x0000000000000006
1210 x7 = 0x0000000000000007
1211 x8 = 0x0000000000000008
1212 x9 = 0x0000000000000009
1213 x10 = 0x0000000000000010
1214 x11 = 0x0000000000000011
1215 x12 = 0x0000000000000012
1216 x13 = 0x0000000000000013
1217 x14 = 0x0000000000000014
1218 x15 = 0x0000000000000015
1219 x16 = 0x0000000000000016
1220 x17 = 0x0000000000000017
1221 x18 = 0x0000000000000018
1222 x19 = 0x0000000000000019
1223 x20 = 0x0000000000000020
1224 x21 = 0x0000000000000021
1225 x22 = 0x0000000000000022
1226 x23 = 0x0000000000000023
1227 x24 = 0x0000000000000024
1228 x25 = 0x0000000000000025
1229 x26 = 0x0000000000000026
1230 x27 = 0x0000000000000027
1231 x28 = 0x0000000000000028
1232 x29 = 0x0000000000000029
1233 x30 = 0x0000000088000b78
1234 scr_el3 = 0x000000000003073d
1235 sctlr_el3 = 0x00000000b0cd183f
1236 cptr_el3 = 0x0000000000000000
1237 tcr_el3 = 0x000000008080351c
1238 daif = 0x00000000000002c0
1239 mair_el3 = 0x00000000004404ff
1240 spsr_el3 = 0x0000000060000349
1241 elr_el3 = 0x0000000088000114
1242 ttbr0_el3 = 0x0000000004018201
1243 esr_el3 = 0x00000000be000000
1244 far_el3 = 0x0000000000000000
1245 spsr_el1 = 0x0000000000000000
1246 elr_el1 = 0x0000000000000000
1247 spsr_abt = 0x0000000000000000
1248 spsr_und = 0x0000000000000000
1249 spsr_irq = 0x0000000000000000
1250 spsr_fiq = 0x0000000000000000
1251 sctlr_el1 = 0x0000000030d00800
1252 actlr_el1 = 0x0000000000000000
1253 cpacr_el1 = 0x0000000000000000
1254 csselr_el1 = 0x0000000000000000
1255 sp_el1 = 0x0000000000000000
1256 esr_el1 = 0x0000000000000000
1257 ttbr0_el1 = 0x0000000000000000
1258 ttbr1_el1 = 0x0000000000000000
1259 mair_el1 = 0x0000000000000000
1260 amair_el1 = 0x0000000000000000
1261 tcr_el1 = 0x0000000000000000
1262 tpidr_el1 = 0x0000000000000000
1263 tpidr_el0 = 0x0000000000000000
1264 tpidrro_el0 = 0x0000000000000000
1265 par_el1 = 0x0000000000000000
1266 mpidr_el1 = 0x0000000080000000
1267 afsr0_el1 = 0x0000000000000000
1268 afsr1_el1 = 0x0000000000000000
1269 contextidr_el1 = 0x0000000000000000
1270 vbar_el1 = 0x0000000000000000
1271 cntp_ctl_el0 = 0x0000000000000000
1272 cntp_cval_el0 = 0x0000000000000000
1273 cntv_ctl_el0 = 0x0000000000000000
1274 cntv_cval_el0 = 0x0000000000000000
1275 cntkctl_el1 = 0x0000000000000000
1276 sp_el0 = 0x0000000004014940
1277 isr_el1 = 0x0000000000000000
1278 dacr32_el2 = 0x0000000000000000
1279 ifsr32_el2 = 0x0000000000000000
1280 icc_hppir0_el1 = 0x00000000000003ff
1281 icc_hppir1_el1 = 0x00000000000003ff
1282 icc_ctlr_el3 = 0x0000000000080400
1283 gicd_ispendr regs (Offsets 0x200-0x278)
1284 Offset Value
1285 0x200: 0x0000000000000000
1286 0x208: 0x0000000000000000
1287 0x210: 0x0000000000000000
1288 0x218: 0x0000000000000000
1289 0x220: 0x0000000000000000
1290 0x228: 0x0000000000000000
1291 0x230: 0x0000000000000000
1292 0x238: 0x0000000000000000
1293 0x240: 0x0000000000000000
1294 0x248: 0x0000000000000000
1295 0x250: 0x0000000000000000
1296 0x258: 0x0000000000000000
1297 0x260: 0x0000000000000000
1298 0x268: 0x0000000000000000
1299 0x270: 0x0000000000000000
1300 0x278: 0x0000000000000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001301
1302Guidelines for Reset Handlers
1303-----------------------------
1304
Dan Handley610e7e12018-03-01 18:44:00 +00001305TF-A implements a framework that allows CPU and platform ports to perform
1306actions very early after a CPU is released from reset in both the cold and warm
1307boot paths. This is done by calling the ``reset_handler()`` function in both
1308the BL1 and BL31 images. It in turn calls the platform and CPU specific reset
1309handling functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001310
1311Details for implementing a CPU specific reset handler can be found in
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001312:ref:`firmware_design_cpu_specific_reset_handling`. Details for implementing a
1313platform specific reset handler can be found in the :ref:`Porting Guide` (see
1314the``plat_reset_handler()`` function).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001315
1316When adding functionality to a reset handler, keep in mind that if a different
1317reset handling behavior is required between the first and the subsequent
1318invocations of the reset handling code, this should be detected at runtime.
1319In other words, the reset handler should be able to detect whether an action has
1320already been performed and act as appropriate. Possible courses of actions are,
1321e.g. skip the action the second time, or undo/redo it.
1322
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05001323.. _configuring-secure-interrupts:
1324
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001325Configuring secure interrupts
1326-----------------------------
1327
1328The GIC driver is responsible for performing initial configuration of secure
1329interrupts on the platform. To this end, the platform is expected to provide the
1330GIC driver (either GICv2 or GICv3, as selected by the platform) with the
1331interrupt configuration during the driver initialisation.
1332
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001333Secure interrupt configuration are specified in an array of secure interrupt
1334properties. In this scheme, in both GICv2 and GICv3 driver data structures, the
1335``interrupt_props`` member points to an array of interrupt properties. Each
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001336element of the array specifies the interrupt number and its attributes
1337(priority, group, configuration). Each element of the array shall be populated
1338by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments:
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001339
Ming Huang1bea7aa2023-02-01 14:03:44 +08001340- 13-bit interrupt number,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001341
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001342- 8-bit interrupt priority,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001343
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001344- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
1345 ``INTR_TYPE_NS``),
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001346
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001347- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
1348 ``GIC_INTR_CFG_EDGE``).
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001349
Paul Beesleyf8640672019-04-12 14:19:42 +01001350.. _firmware_design_cpu_ops_fwk:
1351
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001352CPU specific operations framework
1353---------------------------------
1354
Dan Handley610e7e12018-03-01 18:44:00 +00001355Certain aspects of the Armv8-A architecture are implementation defined,
1356that is, certain behaviours are not architecturally defined, but must be
1357defined and documented by individual processor implementations. TF-A
1358implements a framework which categorises the common implementation defined
1359behaviours and allows a processor to export its implementation of that
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001360behaviour. The categories are:
1361
1362#. Processor specific reset sequence.
1363
1364#. Processor specific power down sequences.
1365
1366#. Processor specific register dumping as a part of crash reporting.
1367
1368#. Errata status reporting.
1369
1370Each of the above categories fulfils a different requirement.
1371
1372#. allows any processor specific initialization before the caches and MMU
1373 are turned on, like implementation of errata workarounds, entry into
1374 the intra-cluster coherency domain etc.
1375
1376#. allows each processor to implement the power down sequence mandated in
1377 its Technical Reference Manual (TRM).
1378
1379#. allows a processor to provide additional information to the developer
1380 in the event of a crash, for example Cortex-A53 has registers which
1381 can expose the data cache contents.
1382
1383#. allows a processor to define a function that inspects and reports the status
1384 of all errata workarounds on that processor.
1385
1386Please note that only 2. is mandated by the TRM.
1387
1388The CPU specific operations framework scales to accommodate a large number of
1389different CPUs during power down and reset handling. The platform can specify
1390any CPU optimization it wants to enable for each CPU. It can also specify
1391the CPU errata workarounds to be applied for each CPU type during reset
1392handling by defining CPU errata compile time macros. Details on these macros
Paul Beesleyf8640672019-04-12 14:19:42 +01001393can be found in the :ref:`Arm CPU Specific Build Macros` document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001394
1395The CPU specific operations framework depends on the ``cpu_ops`` structure which
1396needs to be exported for each type of CPU in the platform. It is defined in
1397``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``,
1398``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1399``cpu_reg_dump()``.
1400
1401The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with
1402suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S``
1403exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform
1404configuration, these CPU specific files must be included in the build by
1405the platform makefile. The generic CPU specific operations framework code exists
1406in ``lib/cpus/aarch64/cpu_helpers.S``.
1407
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001408CPU PCS
1409~~~~~~~
1410
1411All assembly functions in CPU files are asked to follow a modified version of
1412the Procedure Call Standard (PCS) in their internals. This is done to ensure
1413calling these functions from outside the file doesn't unexpectedly corrupt
1414registers in the very early environment and to help the internals to be easier
1415to understand. Please see the :ref:`firmware_design_cpu_errata_implementation`
1416for any function specific restrictions.
1417
1418+--------------+---------------------------------+
1419| register | use |
1420+==============+=================================+
1421| x0 - x15 | scratch |
1422+--------------+---------------------------------+
1423| x16, x17 | do not use (used by the linker) |
1424+--------------+---------------------------------+
1425| x18 | do not use (platform register) |
1426+--------------+---------------------------------+
1427| x19 - x28 | callee saved |
1428+--------------+---------------------------------+
1429| x29, x30 | FP, LR |
1430+--------------+---------------------------------+
1431
1432.. _firmware_design_cpu_specific_reset_handling:
1433
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001434CPU specific Reset Handling
1435~~~~~~~~~~~~~~~~~~~~~~~~~~~
1436
1437After a reset, the state of the CPU when it calls generic reset handler is:
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001438MMU turned off, both instruction and data caches turned off, not part
1439of any coherency domain and no stack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001440
1441The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow
1442the platform to perform any system initialization required and any system
1443errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads
1444the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops``
1445array and returns it. Note that only the part number and implementer fields
1446in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in
1447the returned ``cpu_ops`` is then invoked which executes the required reset
1448handling for that CPU and also any errata workarounds enabled by the platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001449
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001450It should be defined using the ``cpu_reset_func_{start,end}`` macros and its
1451body may only clobber x0 to x14 with x14 being the cpu_rev parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001452
1453CPU specific power down sequence
1454~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1455
1456During the BL31 initialization sequence, the pointer to the matching ``cpu_ops``
1457entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly
1458retrieved during power down sequences.
1459
1460Various CPU drivers register handlers to perform power down at certain power
1461levels for that specific CPU. The PSCI service, upon receiving a power down
1462request, determines the highest power level at which to execute power down
1463sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to
1464pick the right power down handler for the requested level. The function
1465retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further
1466retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the
1467requested power level is higher than what a CPU driver supports, the handler
1468registered for highest level is invoked.
1469
1470At runtime the platform hooks for power down are invoked by the PSCI service to
1471perform platform specific operations during a power down sequence, for example
1472turning off CCI coherency during a cluster power down.
1473
1474CPU specific register reporting during crash
1475~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1476
1477If the crash reporting is enabled in BL31, when a crash occurs, the crash
1478reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching
1479``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in
1480``cpu_ops`` is invoked, which then returns the CPU specific register values to
1481be reported and a pointer to the ASCII list of register names in a format
1482expected by the crash reporting framework.
1483
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001484.. _firmware_design_cpu_errata_implementation:
Paul Beesleyf8640672019-04-12 14:19:42 +01001485
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001486CPU errata implementation
1487~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001488
Dan Handley610e7e12018-03-01 18:44:00 +00001489Errata workarounds for CPUs supported in TF-A are applied during both cold and
1490warm boots, shortly after reset. Individual Errata workarounds are enabled as
1491build options. Some errata workarounds have potential run-time implications;
1492therefore some are enabled by default, others not. Platform ports shall
1493override build options to enable or disable errata as appropriate. The CPU
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001494drivers take care of applying errata workarounds that are enabled and applicable
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001495to a given CPU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001496
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001497Each erratum has a build flag in ``lib/cpus/cpu-ops.mk`` of the form:
1498``ERRATA_<cpu_num>_<erratum_id>``. It also has a short description in
1499:ref:`arm_cpu_macros_errata_workarounds` on when it should apply.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001500
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001501Errata framework
1502^^^^^^^^^^^^^^^^
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001503
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001504The errata framework is a convention and a small library to allow errata to be
1505automatically discovered. It enables compliant errata to be automatically
1506applied and reported at runtime (either by status reporting or the errata ABI).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001507
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001508To write a compliant mitigation for erratum number ``erratum_id`` on a cpu that
1509declared itself (with ``declare_cpu_ops``) as ``cpu_name`` one needs 3 things:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001510
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001511#. A CPU revision checker function: ``check_erratum_<cpu_name>_<erratum_id>``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001512
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001513 It should check whether this erratum applies on this revision of this CPU.
1514 It will be called with the CPU revision as its first parameter (x0) and
1515 should return one of ``ERRATA_APPLIES`` or ``ERRATA_NOT_APPLIES``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001516
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001517 It may only clobber x0 to x4. The rest should be treated as callee-saved.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001518
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001519#. A workaround function: ``erratum_<cpu_name>_<erratum_id>_wa``
1520
1521 It should obtain the cpu revision (with ``cpu_get_rev_var``), call its
1522 revision checker, and perform the mitigation, should the erratum apply.
1523
1524 It may only clobber x0 to x8. The rest should be treated as callee-saved.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001525
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001526#. Register itself to the framework
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001527
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001528 Do this with
1529 ``add_erratum_entry <cpu_name>, ERRATUM(<erratum_id>), <errata_flag>``
1530 where the ``errata_flag`` is the enable flag in ``cpu-ops.mk`` described
1531 above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001532
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001533See the next section on how to do this easily.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001534
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001535.. note::
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001536
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001537 CVEs have the format ``CVE_<year>_<number>``. To fit them in the framework, the
1538 ``erratum_id`` for the checker and the workaround functions become the
1539 ``number`` part of its name and the ``ERRATUM(<number>)`` part of the
1540 registration should instead be ``CVE(<year>, <number>)``. In the extremely
1541 unlikely scenario where a CVE and an erratum numbers clash, the CVE number
1542 should be prefixed with a zero.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001543
Boyan Karatotevd71b5d72023-02-07 15:46:50 +00001544 Also, their build flag should be ``WORKAROUND_CVE_<year>_<number>``.
1545
1546.. note::
1547
1548 AArch32 uses the legacy convention. The checker function has the format
1549 ``check_errata_<erratum_id>`` and the workaround has the format
1550 ``errata_<cpu_number>_<erratum_id>_wa`` where ``cpu_number`` is the shortform
1551 letter and number name of the CPU.
1552
1553 For CVEs the ``erratum_id`` also becomes ``cve_<year>_<number>``.
1554
1555Errata framework helpers
1556^^^^^^^^^^^^^^^^^^^^^^^^
1557
1558Writing these errata involves lots of boilerplate and repetitive code. On
1559AArch64 there are helpers to omit most of this. They are located in
1560``include/lib/cpus/aarch64/cpu_macros.S`` and the preferred way to implement
1561errata. Please see their comments on how to use them.
1562
1563The most common type of erratum workaround, one that just sets a "chicken" bit
1564in some arbitrary register, would have an implementation for the Cortex-A77,
1565erratum #1925769 like::
1566
1567 workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
1568 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8
1569 workaround_reset_end cortex_a77, ERRATUM(1925769)
1570
1571 check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)
1572
1573Status reporting
1574^^^^^^^^^^^^^^^^
1575
1576In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the
1577runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke a generic
1578errata status reporting function. It will read the ``errata_entries`` list of
1579that cpu and will report whether each known erratum was applied and, if not,
1580whether it should have been.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001581
1582Reporting the status of errata workaround is for informational purpose only; it
1583has no functional significance.
1584
1585Memory layout of BL images
1586--------------------------
1587
1588Each bootloader image can be divided in 2 parts:
1589
1590- the static contents of the image. These are data actually stored in the
1591 binary on the disk. In the ELF terminology, they are called ``PROGBITS``
1592 sections;
1593
1594- the run-time contents of the image. These are data that don't occupy any
1595 space in the binary on the disk. The ELF binary just contains some
1596 metadata indicating where these data will be stored at run-time and the
1597 corresponding sections need to be allocated and initialized at run-time.
1598 In the ELF terminology, they are called ``NOBITS`` sections.
1599
1600All PROGBITS sections are grouped together at the beginning of the image,
Dan Handley610e7e12018-03-01 18:44:00 +00001601followed by all NOBITS sections. This is true for all TF-A images and it is
1602governed by the linker scripts. This ensures that the raw binary images are
1603as small as possible. If a NOBITS section was inserted in between PROGBITS
1604sections then the resulting binary file would contain zero bytes in place of
1605this NOBITS section, making the image unnecessarily bigger. Smaller images
1606allow faster loading from the FIP to the main memory.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001607
Samuel Holland31a14e12018-10-17 21:40:18 -05001608For BL31, a platform can specify an alternate location for NOBITS sections
1609(other than immediately following PROGBITS sections) by setting
1610``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and
1611``BL31_NOBITS_LIMIT``.
1612
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001613Linker scripts and symbols
1614~~~~~~~~~~~~~~~~~~~~~~~~~~
1615
1616Each bootloader stage image layout is described by its own linker script. The
1617linker scripts export some symbols into the program symbol table. Their values
Dan Handley610e7e12018-03-01 18:44:00 +00001618correspond to particular addresses. TF-A code can refer to these symbols to
1619figure out the image memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001620
Dan Handley610e7e12018-03-01 18:44:00 +00001621Linker symbols follow the following naming convention in TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001622
1623- ``__<SECTION>_START__``
1624
1625 Start address of a given section named ``<SECTION>``.
1626
1627- ``__<SECTION>_END__``
1628
1629 End address of a given section named ``<SECTION>``. If there is an alignment
1630 constraint on the section's end address then ``__<SECTION>_END__`` corresponds
1631 to the end address of the section's actual contents, rounded up to the right
1632 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the
1633 actual end address of the section's contents.
1634
1635- ``__<SECTION>_UNALIGNED_END__``
1636
1637 End address of a given section named ``<SECTION>`` without any padding or
1638 rounding up due to some alignment constraint.
1639
1640- ``__<SECTION>_SIZE__``
1641
1642 Size (in bytes) of a given section named ``<SECTION>``. If there is an
1643 alignment constraint on the section's end address then ``__<SECTION>_SIZE__``
1644 corresponds to the size of the section's actual contents, rounded up to the
1645 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__``
1646 to know the actual size of the section's contents.
1647
1648- ``__<SECTION>_UNALIGNED_SIZE__``
1649
1650 Size (in bytes) of a given section named ``<SECTION>`` without any padding or
1651 rounding up due to some alignment constraint. In other words,
1652 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``.
1653
Dan Handley610e7e12018-03-01 18:44:00 +00001654Some of the linker symbols are mandatory as TF-A code relies on them to be
1655defined. They are listed in the following subsections. Some of them must be
1656provided for each bootloader stage and some are specific to a given bootloader
1657stage.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001658
1659The linker scripts define some extra, optional symbols. They are not actually
1660used by any code but they help in understanding the bootloader images' memory
1661layout as they are easy to spot in the link map files.
1662
1663Common linker symbols
1664^^^^^^^^^^^^^^^^^^^^^
1665
1666All BL images share the following requirements:
1667
1668- The BSS section must be zero-initialised before executing any C code.
1669- The coherent memory section (if enabled) must be zero-initialised as well.
1670- The MMU setup code needs to know the extents of the coherent and read-only
1671 memory regions to set the right memory attributes. When
1672 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the
1673 read-only memory region is divided between code and data.
1674
1675The following linker symbols are defined for this purpose:
1676
1677- ``__BSS_START__``
1678- ``__BSS_SIZE__``
1679- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary.
1680- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary.
1681- ``__COHERENT_RAM_UNALIGNED_SIZE__``
1682- ``__RO_START__``
1683- ``__RO_END__``
1684- ``__TEXT_START__``
Michal Simek80c530e2023-04-27 14:26:03 +02001685- ``__TEXT_END_UNALIGNED__``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001686- ``__TEXT_END__``
1687- ``__RODATA_START__``
Michal Simek80c530e2023-04-27 14:26:03 +02001688- ``__RODATA_END_UNALIGNED__``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001689- ``__RODATA_END__``
1690
1691BL1's linker symbols
1692^^^^^^^^^^^^^^^^^^^^
1693
1694BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and
1695it is entirely executed in place but it needs some read-write memory for its
1696mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be
1697relocated from ROM to RAM before executing any C code.
1698
1699The following additional linker symbols are defined for BL1:
1700
1701- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code
1702 and ``.data`` section in ROM.
1703- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be
1704 aligned on a 16-byte boundary.
1705- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be
1706 copied over. Must be aligned on a 16-byte boundary.
1707- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM).
1708- ``__BL1_RAM_START__`` Start address of BL1 read-write data.
1709- ``__BL1_RAM_END__`` End address of BL1 read-write data.
1710
1711How to choose the right base addresses for each bootloader stage image
1712~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1713
Dan Handley610e7e12018-03-01 18:44:00 +00001714There is currently no support for dynamic image loading in TF-A. This means
1715that all bootloader images need to be linked against their ultimate runtime
1716locations and the base addresses of each image must be chosen carefully such
1717that images don't overlap each other in an undesired way. As the code grows,
1718the base addresses might need adjustments to cope with the new memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001719
1720The memory layout is completely specific to the platform and so there is no
1721general recipe for choosing the right base addresses for each bootloader image.
1722However, there are tools to aid in understanding the memory layout. These are
1723the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>``
1724being the stage bootloader. They provide a detailed view of the memory usage of
1725each image. Among other useful information, they provide the end address of
1726each image.
1727
1728- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address.
1729- ``bl2.map`` link map file provides ``__BL2_END__`` address.
1730- ``bl31.map`` link map file provides ``__BL31_END__`` address.
1731- ``bl32.map`` link map file provides ``__BL32_END__`` address.
1732
1733For each bootloader image, the platform code must provide its start address
1734as well as a limit address that it must not overstep. The latter is used in the
1735linker scripts to check that the image doesn't grow past that address. If that
1736happens, the linker will issue a message similar to the following:
1737
1738::
1739
1740 aarch64-none-elf-ld: BLx has exceeded its limit.
1741
1742Additionally, if the platform memory layout implies some image overlaying like
1743on FVP, BL31 and TSP need to know the limit address that their PROGBITS
1744sections must not overstep. The platform code must provide those.
1745
Soby Mathew97b1bff2018-09-27 16:46:41 +01001746TF-A does not provide any mechanism to verify at boot time that the memory
1747to load a new image is free to prevent overwriting a previously loaded image.
1748The platform must specify the memory available in the system for all the
1749relevant BL images to be loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001750
1751For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
1752return the region defined by the platform where BL1 intends to load BL2. The
1753``load_image()`` function performs bounds check for the image size based on the
1754base and maximum image size provided by the platforms. Platforms must take
1755this behaviour into account when defining the base/size for each of the images.
1756
Dan Handley610e7e12018-03-01 18:44:00 +00001757Memory layout on Arm development platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001758^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1759
Dan Handley610e7e12018-03-01 18:44:00 +00001760The following list describes the memory layout on the Arm development platforms:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001761
1762- A 4KB page of shared memory is used for communication between Trusted
1763 Firmware and the platform's power controller. This is located at the base of
1764 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader
1765 images is reduced by the size of the shared memory.
1766
1767 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno,
1768 this is also used for the MHU payload when passing messages to and from the
1769 SCP.
1770
Soby Mathew492e2452018-06-06 16:03:10 +01001771- Another 4 KB page is reserved for passing memory layout between BL1 and BL2
1772 and also the dynamic firmware configurations.
1773
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001774- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On
1775 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write
1776 data are relocated to the top of Trusted SRAM at runtime.
1777
Soby Mathew492e2452018-06-06 16:03:10 +01001778- BL2 is loaded below BL1 RW
1779
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001780- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN),
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001781 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
Soby Mathew492e2452018-06-06 16:03:10 +01001782 overwrite BL1 R/W data and BL2. This implies that BL1 global variables
1783 remain valid only until execution reaches the EL3 Runtime Software entry
1784 point during a cold boot.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001785
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001786- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001787 region and transferred to the SCP before being overwritten by EL3 Runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001788 Software.
1789
1790- BL32 (for AArch64) can be loaded in one of the following locations:
1791
1792 - Trusted SRAM
1793 - Trusted DRAM (FVP only)
1794 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
1795 controller)
1796
Soby Mathew492e2452018-06-06 16:03:10 +01001797 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below
1798 BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001799
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001800The location of the BL32 image will result in different memory maps. This is
1801illustrated for both FVP and Juno in the following diagrams, using the TSP as
1802an example.
1803
Paul Beesleyba3ed402019-03-13 16:20:44 +00001804.. note::
1805 Loading the BL32 image in TZC secured DRAM doesn't change the memory
1806 layout of the other images in Trusted SRAM.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001807
Sathees Balya90950092018-11-15 14:22:30 +00001808CONFIG section in memory layouts shown below contains:
1809
1810::
1811
1812 +--------------------+
1813 |bl2_mem_params_descs|
1814 |--------------------|
1815 | fw_configs |
1816 +--------------------+
1817
1818``bl2_mem_params_descs`` contains parameters passed from BL2 to next the
1819BL image during boot.
1820
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001821``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config.
Sathees Balya90950092018-11-15 14:22:30 +00001822
Soby Mathew492e2452018-06-06 16:03:10 +01001823**FVP with TSP in Trusted SRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001824(These diagrams only cover the AArch64 case)
1825
1826::
1827
Soby Mathew492e2452018-06-06 16:03:10 +01001828 DRAM
1829 0xffffffff +----------+
Manish V Badarkhe638ac182023-03-07 10:21:30 +00001830 | EL3 TZC |
1831 0xffe00000 |----------| (secure)
1832 | AP TZC |
1833 0xff000000 +----------+
Soby Mathew492e2452018-06-06 16:03:10 +01001834 : :
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001835 0x82100000 |----------|
Soby Mathew492e2452018-06-06 16:03:10 +01001836 |HW_CONFIG |
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001837 0x82000000 |----------| (non-secure)
Soby Mathew492e2452018-06-06 16:03:10 +01001838 | |
1839 0x80000000 +----------+
1840
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001841 Trusted DRAM
1842 0x08000000 +----------+
1843 |HW_CONFIG |
1844 0x07f00000 |----------|
1845 : :
1846 | |
1847 0x06000000 +----------+
1848
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001849 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001850 0x04040000 +----------+ loaded by BL2 +----------------+
1851 | BL1 (rw) | <<<<<<<<<<<<< | |
1852 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1853 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001854 |----------| <<<<<<<<<<<<< |----------------|
1855 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001856 | | <<<<<<<<<<<<< |----------------|
1857 | | <<<<<<<<<<<<< | BL32 |
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001858 0x04003000 +----------+ +----------------+
Sathees Balya90950092018-11-15 14:22:30 +00001859 | CONFIG |
Soby Mathew492e2452018-06-06 16:03:10 +01001860 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001861 | Shared |
1862 0x04000000 +----------+
1863
1864 Trusted ROM
1865 0x04000000 +----------+
1866 | BL1 (ro) |
1867 0x00000000 +----------+
1868
Soby Mathew492e2452018-06-06 16:03:10 +01001869**FVP with TSP in Trusted DRAM with firmware configs (default option):**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001870
1871::
1872
Soby Mathewb1bf0442018-02-16 14:52:52 +00001873 DRAM
1874 0xffffffff +--------------+
Manish V Badarkhe638ac182023-03-07 10:21:30 +00001875 | EL3 TZC |
1876 0xffe00000 |--------------| (secure)
1877 | AP TZC |
1878 0xff000000 +--------------+
Soby Mathewb1bf0442018-02-16 14:52:52 +00001879 : :
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001880 0x82100000 |--------------|
Soby Mathewb1bf0442018-02-16 14:52:52 +00001881 | HW_CONFIG |
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001882 0x82000000 |--------------| (non-secure)
Soby Mathewb1bf0442018-02-16 14:52:52 +00001883 | |
1884 0x80000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001885
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001886 Trusted DRAM
Soby Mathewb1bf0442018-02-16 14:52:52 +00001887 0x08000000 +--------------+
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001888 | HW_CONFIG |
1889 0x07f00000 |--------------|
1890 : :
1891 | BL32 |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001892 0x06000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001893
Soby Mathewb1bf0442018-02-16 14:52:52 +00001894 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001895 0x04040000 +--------------+ loaded by BL2 +----------------+
1896 | BL1 (rw) | <<<<<<<<<<<<< | |
1897 |--------------| <<<<<<<<<<<<< | BL31 NOBITS |
1898 | BL2 | <<<<<<<<<<<<< | |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001899 |--------------| <<<<<<<<<<<<< |----------------|
1900 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001901 | | +----------------+
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001902 0x04003000 +--------------+
Sathees Balya90950092018-11-15 14:22:30 +00001903 | CONFIG |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001904 0x04001000 +--------------+
1905 | Shared |
1906 0x04000000 +--------------+
1907
1908 Trusted ROM
1909 0x04000000 +--------------+
1910 | BL1 (ro) |
1911 0x00000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001912
Soby Mathew492e2452018-06-06 16:03:10 +01001913**FVP with TSP in TZC-Secured DRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001914
1915::
1916
1917 DRAM
1918 0xffffffff +----------+
Manish V Badarkhe638ac182023-03-07 10:21:30 +00001919 | EL3 TZC |
1920 0xffe00000 |----------| (secure)
1921 | AP TZC |
1922 | (BL32) |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001923 0xff000000 +----------+
1924 | |
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001925 0x82100000 |----------|
Soby Mathew492e2452018-06-06 16:03:10 +01001926 |HW_CONFIG |
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001927 0x82000000 |----------| (non-secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001928 | |
1929 0x80000000 +----------+
1930
Manish V Badarkhe70d8eee2022-04-12 21:11:56 +01001931 Trusted DRAM
1932 0x08000000 +----------+
1933 |HW_CONFIG |
1934 0x7f000000 |----------|
1935 : :
1936 | |
1937 0x06000000 +----------+
1938
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001939 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001940 0x04040000 +----------+ loaded by BL2 +----------------+
1941 | BL1 (rw) | <<<<<<<<<<<<< | |
1942 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1943 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001944 |----------| <<<<<<<<<<<<< |----------------|
1945 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001946 | | +----------------+
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001947 0x04003000 +----------+
Sathees Balya90950092018-11-15 14:22:30 +00001948 | CONFIG |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001949 0x04001000 +----------+
1950 | Shared |
1951 0x04000000 +----------+
1952
1953 Trusted ROM
1954 0x04000000 +----------+
1955 | BL1 (ro) |
1956 0x00000000 +----------+
1957
Soby Mathew492e2452018-06-06 16:03:10 +01001958**Juno with BL32 in Trusted SRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001959
1960::
1961
Manish V Badarkhe638ac182023-03-07 10:21:30 +00001962 DRAM
1963 0xFFFFFFFF +----------+
1964 | SCP TZC |
1965 0xFFE00000 |----------|
1966 | EL3 TZC |
1967 0xFFC00000 |----------| (secure)
1968 | AP TZC |
1969 0xFF000000 +----------+
1970 | |
1971 : : (non-secure)
1972 | |
1973 0x80000000 +----------+
1974
1975
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001976 Flash0
1977 0x0C000000 +----------+
1978 : :
1979 0x0BED0000 |----------|
1980 | BL1 (ro) |
1981 0x0BEC0000 |----------|
1982 : :
1983 0x08000000 +----------+ BL31 is loaded
1984 after SCP_BL2 has
1985 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001986 0x04040000 +----------+ loaded by BL2 +----------------+
1987 | BL1 (rw) | <<<<<<<<<<<<< | |
1988 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1989 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001990 |----------| <<<<<<<<<<<<< |----------------|
1991 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Chris Kayf8fa4652020-03-12 13:50:26 +00001992 | | <<<<<<<<<<<<< |----------------|
Soby Mathew492e2452018-06-06 16:03:10 +01001993 | | <<<<<<<<<<<<< | BL32 |
1994 | | +----------------+
1995 | |
1996 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001997 | MHU |
1998 0x04000000 +----------+
1999
Soby Mathew492e2452018-06-06 16:03:10 +01002000**Juno with BL32 in TZC-secured DRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002001
2002::
2003
2004 DRAM
Manish V Badarkhe638ac182023-03-07 10:21:30 +00002005 0xFFFFFFFF +----------+
2006 | SCP TZC |
2007 0xFFE00000 |----------|
2008 | EL3 TZC |
2009 0xFFC00000 |----------| (secure)
2010 | AP TZC |
2011 | (BL32) |
2012 0xFF000000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002013 | |
2014 : : (non-secure)
2015 | |
2016 0x80000000 +----------+
2017
2018 Flash0
2019 0x0C000000 +----------+
2020 : :
2021 0x0BED0000 |----------|
2022 | BL1 (ro) |
2023 0x0BEC0000 |----------|
2024 : :
2025 0x08000000 +----------+ BL31 is loaded
2026 after SCP_BL2 has
2027 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01002028 0x04040000 +----------+ loaded by BL2 +----------------+
2029 | BL1 (rw) | <<<<<<<<<<<<< | |
2030 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
2031 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002032 |----------| <<<<<<<<<<<<< |----------------|
2033 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Chris Kayf8fa4652020-03-12 13:50:26 +00002034 | | +----------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002035 0x04001000 +----------+
2036 | MHU |
2037 0x04000000 +----------+
2038
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002039.. _firmware_design_fip:
Sathees Balya17d8eed2019-01-30 15:56:44 +00002040
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002041Firmware Image Package (FIP)
2042----------------------------
2043
2044Using a Firmware Image Package (FIP) allows for packing bootloader images (and
Dan Handley610e7e12018-03-01 18:44:00 +00002045potentially other payloads) into a single archive that can be loaded by TF-A
2046from non-volatile platform storage. A driver to load images from a FIP has
2047been added to the storage layer and allows a package to be read from supported
2048platform storage. A tool to create Firmware Image Packages is also provided
2049and described below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002050
2051Firmware Image Package layout
2052~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2053
2054The FIP layout consists of a table of contents (ToC) followed by payload data.
2055The ToC itself has a header followed by one or more table entries. The ToC is
Jett Zhou75566102017-11-24 16:03:58 +08002056terminated by an end marker entry, and since the size of the ToC is 0 bytes,
2057the offset equals the total size of the FIP file. All ToC entries describe some
2058payload data that has been appended to the end of the binary package. With the
2059information provided in the ToC entry the corresponding payload data can be
2060retrieved.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002061
2062::
2063
2064 ------------------
2065 | ToC Header |
2066 |----------------|
2067 | ToC Entry 0 |
2068 |----------------|
2069 | ToC Entry 1 |
2070 |----------------|
2071 | ToC End Marker |
2072 |----------------|
2073 | |
2074 | Data 0 |
2075 | |
2076 |----------------|
2077 | |
2078 | Data 1 |
2079 | |
2080 ------------------
2081
2082The ToC header and entry formats are described in the header file
2083``include/tools_share/firmware_image_package.h``. This file is used by both the
Dan Handley610e7e12018-03-01 18:44:00 +00002084tool and TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002085
2086The ToC header has the following fields:
2087
2088::
2089
2090 `name`: The name of the ToC. This is currently used to validate the header.
2091 `serial_number`: A non-zero number provided by the creation tool
2092 `flags`: Flags associated with this data.
2093 Bits 0-31: Reserved
2094 Bits 32-47: Platform defined
2095 Bits 48-63: Reserved
2096
2097A ToC entry has the following fields:
2098
2099::
2100
2101 `uuid`: All files are referred to by a pre-defined Universally Unique
2102 IDentifier [UUID] . The UUIDs are defined in
2103 `include/tools_share/firmware_image_package.h`. The platform translates
2104 the requested image name into the corresponding UUID when accessing the
2105 package.
2106 `offset_address`: The offset address at which the corresponding payload data
2107 can be found. The offset is calculated from the ToC base address.
2108 `size`: The size of the corresponding payload data in bytes.
Etienne Carriere7421bf12017-08-23 15:43:33 +02002109 `flags`: Flags associated with this entry. None are yet defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002110
2111Firmware Image Package creation tool
2112~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2113
Dan Handley610e7e12018-03-01 18:44:00 +00002114The FIP creation tool can be used to pack specified images into a binary
2115package that can be loaded by TF-A from platform storage. The tool currently
2116only supports packing bootloader images. Additional image definitions can be
2117added to the tool as required.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002118
2119The tool can be found in ``tools/fiptool``.
2120
2121Loading from a Firmware Image Package (FIP)
2122~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2123
2124The Firmware Image Package (FIP) driver can load images from a binary package on
Dan Handley610e7e12018-03-01 18:44:00 +00002125non-volatile platform storage. For the Arm development platforms, this is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002126currently NOR FLASH.
2127
2128Bootloader images are loaded according to the platform policy as specified by
Dan Handley610e7e12018-03-01 18:44:00 +00002129the function ``plat_get_image_source()``. For the Arm development platforms, this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002130means the platform will attempt to load images from a Firmware Image Package
2131located at the start of NOR FLASH0.
2132
Dan Handley610e7e12018-03-01 18:44:00 +00002133The Arm development platforms' policy is to only allow loading of a known set of
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002134images. The platform policy can be modified to allow additional images.
2135
Dan Handley610e7e12018-03-01 18:44:00 +00002136Use of coherent memory in TF-A
2137------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002138
2139There might be loss of coherency when physical memory with mismatched
2140shareability, cacheability and memory attributes is accessed by multiple CPUs
Dan Handley610e7e12018-03-01 18:44:00 +00002141(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs
2142in TF-A during power up/down sequences when coherency, MMU and caches are
2143turned on/off incrementally.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002144
Dan Handley610e7e12018-03-01 18:44:00 +00002145TF-A defines coherent memory as a region of memory with Device nGnRE attributes
2146in the translation tables. The translation granule size in TF-A is 4KB. This
2147is the smallest possible size of the coherent memory region.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002148
2149By default, all data structures which are susceptible to accesses with
2150mismatched attributes from various CPUs are allocated in a coherent memory
Paul Beesleyf8640672019-04-12 14:19:42 +01002151region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory
2152region accesses are Outer Shareable, non-cacheable and they can be accessed with
2153the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of
2154at least an extra page of memory, TF-A is able to work around coherency issues
2155due to mismatched memory attributes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002156
2157The alternative to the above approach is to allocate the susceptible data
2158structures in Normal WriteBack WriteAllocate Inner shareable memory. This
2159approach requires the data structures to be designed so that it is possible to
2160work around the issue of mismatched memory attributes by performing software
2161cache maintenance on them.
2162
Dan Handley610e7e12018-03-01 18:44:00 +00002163Disabling the use of coherent memory in TF-A
2164~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002165
2166It might be desirable to avoid the cost of allocating coherent memory on
Dan Handley610e7e12018-03-01 18:44:00 +00002167platforms which are memory constrained. TF-A enables inclusion of coherent
2168memory in firmware images through the build flag ``USE_COHERENT_MEM``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002169This flag is enabled by default. It can be disabled to choose the second
2170approach described above.
2171
2172The below sections analyze the data structures allocated in the coherent memory
2173region and the changes required to allocate them in normal memory.
2174
2175Coherent memory usage in PSCI implementation
2176~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2177
2178The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
2179tree information for state management of power domains. By default, this data
Dan Handley610e7e12018-03-01 18:44:00 +00002180structure is allocated in the coherent memory region in TF-A because it can be
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002181accessed by multiple CPUs, either with caches enabled or disabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002182
2183.. code:: c
2184
2185 typedef struct non_cpu_pwr_domain_node {
2186 /*
2187 * Index of the first CPU power domain node level 0 which has this node
2188 * as its parent.
2189 */
2190 unsigned int cpu_start_idx;
2191
2192 /*
2193 * Number of CPU power domains which are siblings of the domain indexed
2194 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
2195 * -> cpu_start_idx + ncpus' have this node as their parent.
2196 */
2197 unsigned int ncpus;
2198
2199 /*
2200 * Index of the parent power domain node.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002201 */
2202 unsigned int parent_node;
2203
2204 plat_local_state_t local_state;
2205
2206 unsigned char level;
2207
2208 /* For indexing the psci_lock array*/
2209 unsigned char lock_index;
2210 } non_cpu_pd_node_t;
2211
2212In order to move this data structure to normal memory, the use of each of its
2213fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node``
2214``level`` and ``lock_index`` are only written once during cold boot. Hence removing
2215them from coherent memory involves only doing a clean and invalidate of the
2216cache lines after these fields are written.
2217
2218The field ``local_state`` can be concurrently accessed by multiple CPUs in
2219different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002220mutual exclusion to this field and a clean and invalidate is needed after it
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002221is written.
2222
2223Bakery lock data
2224~~~~~~~~~~~~~~~~
2225
2226The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2227and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is
2228defined as follows:
2229
2230.. code:: c
2231
2232 typedef struct bakery_lock {
2233 /*
2234 * The lock_data is a bit-field of 2 members:
2235 * Bit[0] : choosing. This field is set when the CPU is
2236 * choosing its bakery number.
2237 * Bits[1 - 15] : number. This is the bakery number allocated.
2238 */
2239 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
2240 } bakery_lock_t;
2241
2242It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU
2243fields can be read by all CPUs but only written to by the owning CPU.
2244
2245Depending upon the data cache line size, the per-CPU fields of the
2246``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line.
2247These per-CPU fields can be read and written during lock contention by multiple
2248CPUs with mismatched memory attributes. Since these fields are a part of the
2249lock implementation, they do not have access to any other locking primitive to
2250safeguard against the resulting coherency issues. As a result, simple software
2251cache maintenance is not enough to allocate them in coherent memory. Consider
2252the following example.
2253
2254CPU0 updates its per-CPU field with data cache enabled. This write updates a
2255local cache line which contains a copy of the fields for other CPUs as well. Now
2256CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2257disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
2258its field in any other cache line in the system. This operation will invalidate
2259the update made by CPU0 as well.
2260
2261To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2262has been redesigned. The changes utilise the characteristic of Lamport's Bakery
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002263algorithm mentioned earlier. The bakery_lock structure only allocates the memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002264for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
Chris Kay33bfc5e2023-02-14 11:30:04 +00002265needed for a CPU into a section ``.bakery_lock``. The linker allocates the memory
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002266for other cores by using the total size allocated for the bakery_lock section
2267and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002268perform software cache maintenance on the lock data structure without running
2269into coherency issues associated with mismatched attributes.
2270
2271The bakery lock data structure ``bakery_info_t`` is defined for use when
2272``USE_COHERENT_MEM`` is disabled as follows:
2273
2274.. code:: c
2275
2276 typedef struct bakery_info {
2277 /*
2278 * The lock_data is a bit-field of 2 members:
2279 * Bit[0] : choosing. This field is set when the CPU is
2280 * choosing its bakery number.
2281 * Bits[1 - 15] : number. This is the bakery number allocated.
2282 */
2283 volatile uint16_t lock_data;
2284 } bakery_info_t;
2285
2286The ``bakery_info_t`` represents a single per-CPU field of one lock and
2287the combination of corresponding ``bakery_info_t`` structures for all CPUs in the
2288system represents the complete bakery lock. The view in memory for a system
2289with n bakery locks are:
2290
2291::
2292
Chris Kay33bfc5e2023-02-14 11:30:04 +00002293 .bakery_lock section start
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002294 |----------------|
2295 | `bakery_info_t`| <-- Lock_0 per-CPU field
2296 | Lock_0 | for CPU0
2297 |----------------|
2298 | `bakery_info_t`| <-- Lock_1 per-CPU field
2299 | Lock_1 | for CPU0
2300 |----------------|
2301 | .... |
2302 |----------------|
2303 | `bakery_info_t`| <-- Lock_N per-CPU field
2304 | Lock_N | for CPU0
2305 ------------------
2306 | XXXXX |
2307 | Padding to |
2308 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate
2309 | Granule | continuous memory for remaining CPUs.
2310 ------------------
2311 | `bakery_info_t`| <-- Lock_0 per-CPU field
2312 | Lock_0 | for CPU1
2313 |----------------|
2314 | `bakery_info_t`| <-- Lock_1 per-CPU field
2315 | Lock_1 | for CPU1
2316 |----------------|
2317 | .... |
2318 |----------------|
2319 | `bakery_info_t`| <-- Lock_N per-CPU field
2320 | Lock_N | for CPU1
2321 ------------------
2322 | XXXXX |
2323 | Padding to |
2324 | next Cache WB |
2325 | Granule |
2326 ------------------
2327
2328Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002329operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
Chris Kay33bfc5e2023-02-14 11:30:04 +00002330``.bakery_lock`` section need to be fetched and appropriate cache operations need
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002331to be performed for each access.
2332
Dan Handley610e7e12018-03-01 18:44:00 +00002333On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002334driver (``arm_lock``).
2335
2336Non Functional Impact of removing coherent memory
2337~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2338
2339Removal of the coherent memory region leads to the additional software overhead
2340of performing cache maintenance for the affected data structures. However, since
2341the memory where the data structures are allocated is cacheable, the overhead is
2342mostly mitigated by an increase in performance.
2343
2344There is however a performance impact for bakery locks, due to:
2345
2346- Additional cache maintenance operations, and
2347- Multiple cache line reads for each lock operation, since the bakery locks
2348 for each CPU are distributed across different cache lines.
2349
2350The implementation has been optimized to minimize this additional overhead.
2351Measurements indicate that when bakery locks are allocated in Normal memory, the
2352minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
2353in Device memory the same is 2 micro seconds. The measurements were done on the
Dan Handley610e7e12018-03-01 18:44:00 +00002354Juno Arm development platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002355
2356As mentioned earlier, almost a page of memory can be saved by disabling
2357``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide
2358whether coherent memory should be used. If a platform disables
2359``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can
2360optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the
Paul Beesleyf8640672019-04-12 14:19:42 +01002361:ref:`Porting Guide`). Refer to the reference platform code for examples.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002362
2363Isolating code and read-only data on separate memory pages
2364----------------------------------------------------------
2365
Dan Handley610e7e12018-03-01 18:44:00 +00002366In the Armv8-A VMSA, translation table entries include fields that define the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002367properties of the target memory region, such as its access permissions. The
2368smallest unit of memory that can be addressed by a translation table entry is
2369a memory page. Therefore, if software needs to set different permissions on two
2370memory regions then it needs to map them using different memory pages.
2371
2372The default memory layout for each BL image is as follows:
2373
2374::
2375
2376 | ... |
2377 +-------------------+
2378 | Read-write data |
2379 +-------------------+ Page boundary
2380 | <Padding> |
2381 +-------------------+
2382 | Exception vectors |
2383 +-------------------+ 2 KB boundary
2384 | <Padding> |
2385 +-------------------+
2386 | Read-only data |
2387 +-------------------+
2388 | Code |
2389 +-------------------+ BLx_BASE
2390
Paul Beesleyba3ed402019-03-13 16:20:44 +00002391.. note::
2392 The 2KB alignment for the exception vectors is an architectural
2393 requirement.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002394
2395The read-write data start on a new memory page so that they can be mapped with
2396read-write permissions, whereas the code and read-only data below are configured
2397as read-only.
2398
2399However, the read-only data are not aligned on a page boundary. They are
2400contiguous to the code. Therefore, the end of the code section and the beginning
2401of the read-only data one might share a memory page. This forces both to be
2402mapped with the same memory attributes. As the code needs to be executable, this
2403means that the read-only data stored on the same memory page as the code are
2404executable as well. This could potentially be exploited as part of a security
2405attack.
2406
2407TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and
2408read-only data on separate memory pages. This in turn allows independent control
2409of the access permissions for the code and read-only data. In this case,
2410platform code gets a finer-grained view of the image layout and can
2411appropriately map the code region as executable and the read-only data as
2412execute-never.
2413
2414This has an impact on memory footprint, as padding bytes need to be introduced
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002415between the code and read-only data to ensure the segregation of the two. To
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002416limit the memory cost, this flag also changes the memory layout such that the
2417code and exception vectors are now contiguous, like so:
2418
2419::
2420
2421 | ... |
2422 +-------------------+
2423 | Read-write data |
2424 +-------------------+ Page boundary
2425 | <Padding> |
2426 +-------------------+
2427 | Read-only data |
2428 +-------------------+ Page boundary
2429 | <Padding> |
2430 +-------------------+
2431 | Exception vectors |
2432 +-------------------+ 2 KB boundary
2433 | <Padding> |
2434 +-------------------+
2435 | Code |
2436 +-------------------+ BLx_BASE
2437
2438With this more condensed memory layout, the separation of read-only data will
2439add zero or one page to the memory footprint of each BL image. Each platform
2440should consider the trade-off between memory footprint and security.
2441
Dan Handley610e7e12018-03-01 18:44:00 +00002442This build flag is disabled by default, minimising memory footprint. On Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002443platforms, it is enabled.
2444
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002445Publish and Subscribe Framework
2446-------------------------------
2447
2448The Publish and Subscribe Framework allows EL3 components to define and publish
2449events, to which other EL3 components can subscribe.
2450
2451The following macros are provided by the framework:
2452
2453- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument,
2454 the event name, which must be a valid C identifier. All calls to
2455 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file
2456 ``pubsub_events.h``.
2457
2458- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating
2459 subscribed handlers and calling them in turn. The handlers will be passed the
2460 parameter ``arg``. The expected use-case is to broadcast an event.
2461
2462- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value
2463 ``NULL`` is passed to subscribed handlers.
2464
2465- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to
2466 subscribe to ``event``. The handler will be executed whenever the ``event``
2467 is published.
2468
2469- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers
2470 subscribed for ``event``. ``subscriber`` must be a local variable of type
2471 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during
2472 iteration. This macro can be used for those patterns that none of the
2473 ``PUBLISH_EVENT_*()`` macros cover.
2474
2475Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will
2476result in build error. Subscribing to an undefined event however won't.
2477
2478Subscribed handlers must be of type ``pubsub_cb_t``, with following function
2479signature:
2480
Paul Beesley493e3492019-03-13 15:11:04 +00002481.. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002482
2483 typedef void* (*pubsub_cb_t)(const void *arg);
2484
2485There may be arbitrary number of handlers registered to the same event. The
2486order in which subscribed handlers are notified when that event is published is
2487not defined. Subscribed handlers may be executed in any order; handlers should
2488not assume any relative ordering amongst them.
2489
2490Publishing an event on a PE will result in subscribed handlers executing on that
2491PE only; it won't cause handlers to execute on a different PE.
2492
2493Note that publishing an event on a PE blocks until all the subscribed handlers
2494finish executing on the PE.
2495
Dan Handley610e7e12018-03-01 18:44:00 +00002496TF-A generic code publishes and subscribes to some events within. Platform
2497ports are discouraged from subscribing to them. These events may be withdrawn,
2498renamed, or have their semantics altered in the future. Platforms may however
2499register, publish, and subscribe to platform-specific events.
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01002500
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002501Publish and Subscribe Example
2502~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2503
2504A publisher that wants to publish event ``foo`` would:
2505
2506- Define the event ``foo`` in the ``pubsub_events.h``.
2507
Paul Beesley493e3492019-03-13 15:11:04 +00002508 .. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002509
2510 REGISTER_PUBSUB_EVENT(foo);
2511
2512- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to
2513 publish the event at the appropriate path and time of execution.
2514
2515A subscriber that wants to subscribe to event ``foo`` published above would
2516implement:
2517
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002518.. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002519
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002520 void *foo_handler(const void *arg)
2521 {
2522 void *result;
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002523
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002524 /* Do handling ... */
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002525
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002526 return result;
2527 }
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002528
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002529 SUBSCRIBE_TO_EVENT(foo, foo_handler);
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002530
Daniel Boulby468f0d72018-09-18 11:45:51 +01002531
2532Reclaiming the BL31 initialization code
2533~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2534
2535A significant amount of the code used for the initialization of BL31 is never
2536needed again after boot time. In order to reduce the runtime memory
2537footprint, the memory used for this code can be reclaimed after initialization
2538has finished and be used for runtime data.
2539
2540The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code
2541with a ``.text.init.*`` attribute which can be filtered and placed suitably
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002542within the BL image for later reclamation by the platform. The platform can
2543specify the filter and the memory region for this init section in BL31 via the
Daniel Boulby468f0d72018-09-18 11:45:51 +01002544plat.ld.S linker script. For example, on the FVP, this section is placed
2545overlapping the secondary CPU stacks so that after the cold boot is done, this
2546memory can be reclaimed for the stacks. The init memory section is initially
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002547mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has
Daniel Boulby468f0d72018-09-18 11:45:51 +01002548completed, the FVP changes the attributes of this section to ``RW``,
2549``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes
2550are changed within the ``bl31_plat_runtime_setup`` platform hook. The init
2551section section can be reclaimed for any data which is accessed after cold
2552boot initialization and it is upto the platform to make the decision.
2553
Paul Beesleyf8640672019-04-12 14:19:42 +01002554.. _firmware_design_pmf:
2555
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002556Performance Measurement Framework
2557---------------------------------
2558
2559The Performance Measurement Framework (PMF) facilitates collection of
Dan Handley610e7e12018-03-01 18:44:00 +00002560timestamps by registered services and provides interfaces to retrieve them
2561from within TF-A. A platform can choose to expose appropriate SMCs to
2562retrieve these collected timestamps.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002563
2564By default, the global physical counter is used for the timestamp
2565value and is read via ``CNTPCT_EL0``. The framework allows to retrieve
2566timestamps captured by other CPUs.
2567
2568Timestamp identifier format
2569~~~~~~~~~~~~~~~~~~~~~~~~~~~
2570
2571A PMF timestamp is uniquely identified across the system via the
2572timestamp ID or ``tid``. The ``tid`` is composed as follows:
2573
2574::
2575
2576 Bits 0-7: The local timestamp identifier.
2577 Bits 8-9: Reserved.
2578 Bits 10-15: The service identifier.
2579 Bits 16-31: Reserved.
2580
2581#. The service identifier. Each PMF service is identified by a
2582 service name and a service identifier. Both the service name and
2583 identifier are unique within the system as a whole.
2584
2585#. The local timestamp identifier. This identifier is unique within a given
2586 service.
2587
2588Registering a PMF service
2589~~~~~~~~~~~~~~~~~~~~~~~~~
2590
2591To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h``
2592is used. The arguments required are the service name, the service ID,
2593the total number of local timestamps to be captured and a set of flags.
2594
2595The ``flags`` field can be specified as a bitwise-OR of the following values:
2596
2597::
2598
2599 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval.
2600 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console.
2601
2602The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured
2603timestamps in a PMF specific linker section at build time.
2604Additionally, it defines necessary functions to capture and
2605retrieve a particular timestamp for the given service at runtime.
2606
Dan Handley610e7e12018-03-01 18:44:00 +00002607The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps
2608from within TF-A. In order to retrieve timestamps from outside of TF-A, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002609``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro
2610accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()``
2611macro but additionally supports retrieving timestamps using SMCs.
2612
2613Capturing a timestamp
2614~~~~~~~~~~~~~~~~~~~~~
2615
2616PMF timestamps are stored in a per-service timestamp region. On a
2617system with multiple CPUs, each timestamp is captured and stored
2618in a per-CPU cache line aligned memory region.
2619
2620Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be
2621used to capture a timestamp at the location where it is used. The macro
2622takes the service name, a local timestamp identifier and a flag as arguments.
2623
2624The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which
2625instructs PMF to do cache maintenance following the capture. Cache
2626maintenance is required if any of the service's timestamps are captured
2627with data cache disabled.
2628
2629To capture a timestamp in assembly code, the caller should use
2630``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to
2631calculate the address of where the timestamp would be stored. The
2632caller should then read ``CNTPCT_EL0`` register to obtain the timestamp
2633and store it at the determined address for later retrieval.
2634
2635Retrieving a timestamp
2636~~~~~~~~~~~~~~~~~~~~~~
2637
Dan Handley610e7e12018-03-01 18:44:00 +00002638From within TF-A, timestamps for individual CPUs can be retrieved using either
2639``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros.
2640These macros accept the CPU's MPIDR value, or its ordinal position
2641respectively.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002642
Dan Handley610e7e12018-03-01 18:44:00 +00002643From outside TF-A, timestamps for individual CPUs can be retrieved by calling
2644into ``pmf_smc_handler()``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002645
Paul Beesley493e3492019-03-13 15:11:04 +00002646::
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002647
2648 Interface : pmf_smc_handler()
2649 Argument : unsigned int smc_fid, u_register_t x1,
2650 u_register_t x2, u_register_t x3,
2651 u_register_t x4, void *cookie,
2652 void *handle, u_register_t flags
2653 Return : uintptr_t
2654
2655 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32`
2656 when the caller of the SMC is running in AArch32 mode
2657 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode.
2658 x1: Timestamp identifier.
2659 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved.
2660 This can be the `mpidr` of a different core to the one initiating
2661 the SMC. In that case, service specific cache maintenance may be
2662 required to ensure the updated copy of the timestamp is returned.
2663 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If
2664 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a
2665 cache invalidate before reading the timestamp. This ensures
2666 an updated copy is returned.
2667
2668The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused
2669in this implementation.
2670
2671PMF code structure
2672~~~~~~~~~~~~~~~~~~
2673
2674#. ``pmf_main.c`` consists of core functions that implement service registration,
2675 initialization, storing, dumping and retrieving timestamps.
2676
2677#. ``pmf_smc.c`` contains the SMC handling for registered PMF services.
2678
2679#. ``pmf.h`` contains the public interface to Performance Measurement Framework.
2680
2681#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in
2682 assembly code.
2683
2684#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``.
2685
Dan Handley610e7e12018-03-01 18:44:00 +00002686Armv8-A Architecture Extensions
2687-------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002688
Dan Handley610e7e12018-03-01 18:44:00 +00002689TF-A makes use of Armv8-A Architecture Extensions where applicable. This
2690section lists the usage of Architecture Extensions, and build flags
2691controlling them.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002692
Manish Pandeyacdaac22023-05-12 14:51:39 +01002693Build options
2694~~~~~~~~~~~~~
2695
2696``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR``
2697
2698These build options serve dual purpose
2699
2700- Determine the architecture extension support in TF-A build: All the mandatory
2701 architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included
2702 and unconditionally enabled by TF-A build system.
2703
Govindraj Raja81525652023-07-18 13:55:33 -05002704- ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` are passed to a march.mk build utility
2705 this will try to come up with an appropriate -march value to be passed to compiler
2706 by probing the compiler and checking what's supported by the compiler and what's best
2707 that can be used. But if platform provides a ``MARCH_DIRECTIVE`` then it will used
2708 directly and compiler probing will be skipped.
Manish Pandeyacdaac22023-05-12 14:51:39 +01002709
2710The build system requires that the platform provides a valid numeric value based on
2711CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture.
2712Subsequent Arm Architecture versions also support extensions which were introduced
2713in previous versions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002714
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002715.. seealso:: :ref:`Build Options`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002716
2717For details on the Architecture Extension and available features, please refer
2718to the respective Architecture Extension Supplement.
2719
Dan Handley610e7e12018-03-01 18:44:00 +00002720Armv8.1-A
2721~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002722
2723This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
2724``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1.
2725
Soby Mathewad042012019-09-25 14:03:41 +01002726- By default, a load-/store-exclusive instruction pair is used to implement
2727 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the
2728 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction.
2729 Notice this instruction is only available in AArch64 execution state, so
2730 the option is only available to AArch64 builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002731
Dan Handley610e7e12018-03-01 18:44:00 +00002732Armv8.2-A
2733~~~~~~~~~
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002734
Antonio Nino Diaz633703a2019-02-19 13:14:06 +00002735- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the
2736 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple
Sandrine Bailleuxfee6e262018-01-29 14:48:15 +01002737 Processing Elements in the same Inner Shareable domain use the same
2738 translation table entries for a given stage of translation for a particular
2739 translation regime.
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002740
Jeenu Viswambharancbad6612018-08-15 14:29:29 +01002741Armv8.3-A
2742~~~~~~~~~
2743
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00002744- Pointer authentication features of Armv8.3-A are unconditionally enabled in
2745 the Non-secure world so that lower ELs are allowed to use them without
2746 causing a trap to EL3.
2747
2748 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS``
2749 must be set to 1. This will add all pointer authentication system registers
2750 to the context that is saved when doing a world switch.
Jeenu Viswambharancbad6612018-08-15 14:29:29 +01002751
Alexei Fedorov2831d582019-03-13 11:05:07 +00002752 The TF-A itself has support for pointer authentication at runtime
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002753 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002754 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1,
2755 BL2, BL31, and the TSP if it is used.
2756
Alexei Fedorov2831d582019-03-13 11:05:07 +00002757 Note that Pointer Authentication is enabled for Non-secure world irrespective
2758 of the value of these build flags if the CPU supports it.
2759
Alexei Fedorovb567e5d2019-03-11 16:51:47 +00002760 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of
2761 enabling PAuth is lower because the compiler will use the optimized
2762 PAuth instructions rather than the backwards-compatible ones.
2763
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002764Armv8.5-A
2765~~~~~~~~~
2766
2767- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
Manish Pandey34a305e2021-10-21 21:53:49 +01002768 option set to 1. This option defaults to 0.
Justin Chadwell55c73512019-07-18 16:16:32 +01002769
2770- Memory Tagging Extension feature is unconditionally enabled for both worlds
2771 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is
2772 implemented at all ELs, it is unconditionally enabled for only the normal
2773 world. To enable it for the secure world as well, the build option
Govindraj Raja24d3a4e2023-12-21 13:57:49 -06002774 ``ENABLE_FEAT_MTE`` is required. If the hardware does not implement
Justin Chadwell55c73512019-07-18 16:16:32 +01002775 MTE support at all, it is always disabled, no matter what build options
2776 are used.
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002777
Dan Handley610e7e12018-03-01 18:44:00 +00002778Armv7-A
2779~~~~~~~
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002780
2781This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7.
2782
Dan Handley610e7e12018-03-01 18:44:00 +00002783There are several Armv7-A extensions available. Obviously the TrustZone
2784extension is mandatory to support the TF-A bootloader and runtime services.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002785
Dan Handley610e7e12018-03-01 18:44:00 +00002786Platform implementing an Armv7-A system can to define from its target
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002787Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002788``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002789Cortex-A15 target.
2790
2791Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support.
Paul Beesleyf2ec7142019-10-04 16:17:46 +00002792Note that using neon at runtime has constraints on non secure world context.
Dan Handley610e7e12018-03-01 18:44:00 +00002793TF-A does not yet provide VFP context management.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002794
2795Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set
2796the toolchain target architecture directive.
2797
2798Platform may choose to not define straight the toolchain target architecture
Govindraj Rajacd10c6e2023-05-30 16:52:15 -05002799directive by defining ``MARCH_DIRECTIVE``.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002800I.e:
2801
Paul Beesley493e3492019-03-13 15:11:04 +00002802.. code:: make
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002803
Govindraj Raja81525652023-07-18 13:55:33 -05002804 MARCH_DIRECTIVE := -march=armv7-a
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002805
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002806Code Structure
2807--------------
2808
Dan Handley610e7e12018-03-01 18:44:00 +00002809TF-A code is logically divided between the three boot loader stages mentioned
2810in the previous sections. The code is also divided into the following
2811categories (present as directories in the source code):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002812
2813- **Platform specific.** Choice of architecture specific code depends upon
2814 the platform.
2815- **Common code.** This is platform and architecture agnostic code.
2816- **Library code.** This code comprises of functionality commonly used by all
2817 other code. The PSCI implementation and other EL3 runtime frameworks reside
2818 as Library components.
2819- **Stage specific.** Code specific to a boot stage.
2820- **Drivers.**
2821- **Services.** EL3 runtime services (eg: SPD). Specific SPD services
2822 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``).
2823
2824Each boot loader stage uses code from one or more of the above mentioned
2825categories. Based upon the above, the code layout looks like this:
2826
2827::
2828
2829 Directory Used by BL1? Used by BL2? Used by BL31?
2830 bl1 Yes No No
2831 bl2 No Yes No
2832 bl31 No No Yes
2833 plat Yes Yes Yes
2834 drivers Yes No Yes
2835 common Yes Yes Yes
2836 lib Yes Yes Yes
2837 services No No Yes
2838
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002839The build system provides a non configurable build option IMAGE_BLx for each
2840boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be
Dan Handley610e7e12018-03-01 18:44:00 +00002841defined by the build system. This enables TF-A to compile certain code only
2842for specific boot loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002843
2844All assembler files have the ``.S`` extension. The linker source files for each
2845boot stage have the extension ``.ld.S``. These are processed by GCC to create the
2846linker scripts which have the extension ``.ld``.
2847
2848FDTs provide a description of the hardware platform and are used by the Linux
2849kernel at boot time. These can be found in the ``fdts`` directory.
2850
Paul Beesleyf8640672019-04-12 14:19:42 +01002851.. rubric:: References
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002852
Paul Beesleyf8640672019-04-12 14:19:42 +01002853- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_
2854
Manish V Badarkhe9d24e9b2023-06-15 09:14:33 +01002855- `PSCI`_
Paul Beesleyf8640672019-04-12 14:19:42 +01002856
Sandrine Bailleuxd9202df2020-04-17 14:06:52 +02002857- `SMC Calling Convention`_
Paul Beesleyf8640672019-04-12 14:19:42 +01002858
2859- :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002860
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Govindraj Raja24d3a4e2023-12-21 13:57:49 -06002863*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002864
laurenw-arm03e7e612020-04-16 10:02:17 -05002865.. _SMCCC: https://developer.arm.com/docs/den0028/latest
Manish V Badarkhe9d24e9b2023-06-15 09:14:33 +01002866.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
Petre-Ionut Tudor620a7022019-09-27 15:13:21 +01002867.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest
laurenw-arm03e7e612020-04-16 10:02:17 -05002868.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
Sandrine Bailleux30918422019-04-24 10:41:24 +02002869.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
Zelalem Aweke023b1a42021-10-21 13:59:45 -05002870.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture
Manish Pandey493bdc42023-07-21 13:08:53 +01002871.. _AArch64 exception vector table: https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002872
Paul Beesley814f8c02019-03-13 15:49:27 +00002873.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png