blob: 116bd5d8649149130a68d5869b2c075b84ab7d70 [file] [log] [blame]
Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Nicolas Le Bayon8ce825f2021-05-18 10:01:30 +02002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_DEF_H
8#define STM32MP1_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010011#include <drivers/st/stm32mp1_rcc.h>
12#include <dt-bindings/clock/stm32mp1-clks.h>
13#include <dt-bindings/reset/stm32mp1-resets.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils_def.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020016
Julius Werner53456fc2019-07-09 13:49:11 -070017#ifndef __ASSEMBLER__
Yann Gautier091eab52019-06-04 18:06:34 +020018#include <drivers/st/bsec.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010019#include <drivers/st/stm32mp1_clk.h>
20
Yann Gautier57e282b2019-01-07 11:17:24 +010021#include <boot_api.h>
Lionel Debieve7bd96f42019-09-03 12:22:23 +020022#include <stm32mp_auth.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010023#include <stm32mp_common.h>
24#include <stm32mp_dt.h>
Yann Gautierc7374052019-06-04 18:02:37 +020025#include <stm32mp1_dbgmcu.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010026#include <stm32mp1_private.h>
Etienne Carriere316d6342019-12-02 10:08:48 +010027#include <stm32mp1_shared_resources.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010028#endif
29
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020030#if !STM32MP_USE_STM32IMAGE
31#include "stm32mp1_fip_def.h"
32#else /* STM32MP_USE_STM32IMAGE */
33#include "stm32mp1_stm32image_def.h"
34#endif /* STM32MP_USE_STM32IMAGE */
35
Yann Gautier4b0c72a2018-07-16 10:54:09 +020036/*******************************************************************************
Yann Gautierc7374052019-06-04 18:02:37 +020037 * CHIP ID
38 ******************************************************************************/
Yann Gautier16188f32020-02-12 15:38:34 +010039#if STM32MP13
40#define STM32MP1_CHIP_ID U(0x501)
41
42#define STM32MP135C_PART_NB U(0x05010000)
43#define STM32MP135A_PART_NB U(0x05010001)
44#define STM32MP133C_PART_NB U(0x050100C0)
45#define STM32MP133A_PART_NB U(0x050100C1)
46#define STM32MP131C_PART_NB U(0x050106C8)
47#define STM32MP131A_PART_NB U(0x050106C9)
48#define STM32MP135F_PART_NB U(0x05010800)
49#define STM32MP135D_PART_NB U(0x05010801)
50#define STM32MP133F_PART_NB U(0x050108C0)
51#define STM32MP133D_PART_NB U(0x050108C1)
52#define STM32MP131F_PART_NB U(0x05010EC8)
53#define STM32MP131D_PART_NB U(0x05010EC9)
54#endif
55#if STM32MP15
Yann Gautiera0a6ff62021-05-10 16:05:18 +020056#define STM32MP1_CHIP_ID U(0x500)
57
Yann Gautierc7374052019-06-04 18:02:37 +020058#define STM32MP157C_PART_NB U(0x05000000)
59#define STM32MP157A_PART_NB U(0x05000001)
60#define STM32MP153C_PART_NB U(0x05000024)
61#define STM32MP153A_PART_NB U(0x05000025)
62#define STM32MP151C_PART_NB U(0x0500002E)
63#define STM32MP151A_PART_NB U(0x0500002F)
Lionel Debieve7b64e3e2019-05-17 16:01:18 +020064#define STM32MP157F_PART_NB U(0x05000080)
65#define STM32MP157D_PART_NB U(0x05000081)
66#define STM32MP153F_PART_NB U(0x050000A4)
67#define STM32MP153D_PART_NB U(0x050000A5)
68#define STM32MP151F_PART_NB U(0x050000AE)
69#define STM32MP151D_PART_NB U(0x050000AF)
Yann Gautier16188f32020-02-12 15:38:34 +010070#endif
Yann Gautierc7374052019-06-04 18:02:37 +020071
72#define STM32MP1_REV_B U(0x2000)
Yann Gautier0fd6e232021-08-25 14:40:12 +020073#if STM32MP13
Yann Gautier06cc7912022-05-09 17:01:11 +020074#define STM32MP1_REV_Y U(0x1003)
Yann Gautier0fd6e232021-08-25 14:40:12 +020075#define STM32MP1_REV_Z U(0x1001)
76#endif
77#if STM32MP15
Lionel Debieve2d64b532019-06-25 10:40:37 +020078#define STM32MP1_REV_Z U(0x2001)
Yann Gautier0fd6e232021-08-25 14:40:12 +020079#endif
Yann Gautierc7374052019-06-04 18:02:37 +020080
81/*******************************************************************************
82 * PACKAGE ID
83 ******************************************************************************/
Yann Gautier16188f32020-02-12 15:38:34 +010084#if STM32MP15
Yann Gautierc7374052019-06-04 18:02:37 +020085#define PKG_AA_LFBGA448 U(4)
86#define PKG_AB_LFBGA354 U(3)
87#define PKG_AC_TFBGA361 U(2)
88#define PKG_AD_TFBGA257 U(1)
Yann Gautier16188f32020-02-12 15:38:34 +010089#endif
Yann Gautierc7374052019-06-04 18:02:37 +020090
91/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +020092 * STM32MP1 memory map related constants
93 ******************************************************************************/
Lionel Debieve7bd96f42019-09-03 12:22:23 +020094#define STM32MP_ROM_BASE U(0x00000000)
95#define STM32MP_ROM_SIZE U(0x00020000)
Yann Gautier3c93a252021-09-15 15:12:57 +020096#define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020097
Yann Gautier15e84832020-02-03 17:48:07 +010098#if STM32MP13
99#define STM32MP_SYSRAM_BASE U(0x2FFE0000)
100#define STM32MP_SYSRAM_SIZE U(0x00020000)
101#define SRAM1_BASE U(0x30000000)
102#define SRAM1_SIZE U(0x00004000)
103#define SRAM2_BASE U(0x30004000)
104#define SRAM2_SIZE U(0x00002000)
105#define SRAM3_BASE U(0x30006000)
106#define SRAM3_SIZE U(0x00002000)
Yann Gautier84d994b2020-04-14 18:08:50 +0200107#define SRAMS_BASE SRAM1_BASE
108#define SRAMS_SIZE_2MB_ALIGNED U(0x00200000)
Yann Gautier15e84832020-02-03 17:48:07 +0100109#endif /* STM32MP13 */
110#if STM32MP15
Yann Gautiera2e2a302019-02-14 11:13:39 +0100111#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
112#define STM32MP_SYSRAM_SIZE U(0x00040000)
Yann Gautier15e84832020-02-03 17:48:07 +0100113#endif /* STM32MP15 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200114
Etienne Carriere72369b12019-12-08 08:17:56 +0100115#define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
116#define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
117 STM32MP_SYSRAM_SIZE - \
118 STM32MP_NS_SYSRAM_SIZE)
119
Etienne Carriere34f0e932020-07-16 17:36:18 +0200120#define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
121#define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
122
Etienne Carriere72369b12019-12-08 08:17:56 +0100123#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
124#define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
125 STM32MP_NS_SYSRAM_SIZE)
126
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200127/* DDR configuration */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100128#define STM32MP_DDR_BASE U(0xC0000000)
129#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200130
131/* DDR power initializations */
Julius Werner53456fc2019-07-09 13:49:11 -0700132#ifndef __ASSEMBLER__
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200133enum ddr_type {
134 STM32MP_DDR3,
135 STM32MP_LPDDR2,
Yann Gautier917a00c2019-04-16 16:20:58 +0200136 STM32MP_LPDDR3
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200137};
138#endif
139
140/* Section used inside TF binaries */
Yann Gautier84d994b2020-04-14 18:08:50 +0200141#if STM32MP13
142/* 512 Octets reserved for header */
143#define STM32MP_HEADER_RESERVED_SIZE U(0x200)
144
145#define STM32MP_BINARY_BASE STM32MP_SEC_SYSRAM_BASE
146
147#define STM32MP_BINARY_SIZE STM32MP_SEC_SYSRAM_SIZE
148#endif
149#if STM32MP15
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200150#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200151/* 256 Octets reserved for header */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100152#define STM32MP_HEADER_SIZE U(0x00000100)
Yann Gautiera1ee9ed2020-09-17 11:30:18 +0200153/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
154#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200155
Etienne Carriere72369b12019-12-08 08:17:56 +0100156#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100157 STM32MP_PARAM_LOAD_SIZE + \
158 STM32MP_HEADER_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200159
Etienne Carriere72369b12019-12-08 08:17:56 +0100160#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100161 (STM32MP_PARAM_LOAD_SIZE + \
162 STM32MP_HEADER_SIZE))
Yann Gautier84d994b2020-04-14 18:08:50 +0200163#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200164
Yann Gautierebc765f2020-01-16 18:50:51 +0100165/* BL2 and BL32/sp_min require finer granularity tables */
166#if defined(IMAGE_BL2)
167#define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */
168#endif
169
170#if defined(IMAGE_BL32)
171#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
172#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200173
174/*
175 * MAX_MMAP_REGIONS is usually:
176 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
177 */
Yann Gautier9d135e42018-07-16 19:36:06 +0200178#if defined(IMAGE_BL2)
Yann Gautierebc765f2020-01-16 18:50:51 +0100179 #if STM32MP_USB_PROGRAMMER
180 #define MAX_MMAP_REGIONS 8
181 #else
182 #define MAX_MMAP_REGIONS 7
183 #endif
Yann Gautier9d135e42018-07-16 19:36:06 +0200184#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200185
Patrick Delaunay8bed83d2021-04-13 14:44:48 +0200186#if STM32MP13
187#define STM32MP_BL33_BASE STM32MP_DDR_BASE
188#endif
189#if STM32MP15
Yann Gautiera2e2a302019-02-14 11:13:39 +0100190#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
Patrick Delaunay8bed83d2021-04-13 14:44:48 +0200191#endif
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200192#define STM32MP_BL33_MAX_SIZE U(0x400000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200193
Lionel Debieve402a46b2019-11-04 12:28:15 +0100194/* Define maximum page size for NAND devices */
195#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
196
Lionel Debieve129f6512021-04-13 17:11:00 +0200197/* Define location for the MTD scratch buffer */
198#if STM32MP13
199#define STM32MP_MTD_BUFFER (SRAM1_BASE + \
200 SRAM1_SIZE - \
201 PLATFORM_MTD_MAX_PAGE_SIZE)
202#endif
Lionel Debieve402a46b2019-11-04 12:28:15 +0100203/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200204 * STM32MP1 device/io map related constants (used for MMU)
205 ******************************************************************************/
206#define STM32MP1_DEVICE1_BASE U(0x40000000)
207#define STM32MP1_DEVICE1_SIZE U(0x40000000)
208
209#define STM32MP1_DEVICE2_BASE U(0x80000000)
210#define STM32MP1_DEVICE2_SIZE U(0x40000000)
211
212/*******************************************************************************
213 * STM32MP1 RCC
214 ******************************************************************************/
215#define RCC_BASE U(0x50000000)
216
217/*******************************************************************************
218 * STM32MP1 PWR
219 ******************************************************************************/
220#define PWR_BASE U(0x50001000)
221
222/*******************************************************************************
Yann Gautier038bff22019-01-17 19:17:47 +0100223 * STM32MP1 GPIO
224 ******************************************************************************/
225#define GPIOA_BASE U(0x50002000)
226#define GPIOB_BASE U(0x50003000)
227#define GPIOC_BASE U(0x50004000)
228#define GPIOD_BASE U(0x50005000)
229#define GPIOE_BASE U(0x50006000)
230#define GPIOF_BASE U(0x50007000)
231#define GPIOG_BASE U(0x50008000)
232#define GPIOH_BASE U(0x50009000)
233#define GPIOI_BASE U(0x5000A000)
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100234#if STM32MP15
Yann Gautier038bff22019-01-17 19:17:47 +0100235#define GPIOJ_BASE U(0x5000B000)
236#define GPIOK_BASE U(0x5000C000)
237#define GPIOZ_BASE U(0x54004000)
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100238#endif
Yann Gautier038bff22019-01-17 19:17:47 +0100239#define GPIO_BANK_OFFSET U(0x1000)
240
241/* Bank IDs used in GPIO driver API */
242#define GPIO_BANK_A U(0)
243#define GPIO_BANK_B U(1)
244#define GPIO_BANK_C U(2)
245#define GPIO_BANK_D U(3)
246#define GPIO_BANK_E U(4)
247#define GPIO_BANK_F U(5)
248#define GPIO_BANK_G U(6)
249#define GPIO_BANK_H U(7)
250#define GPIO_BANK_I U(8)
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100251#if STM32MP15
Yann Gautier038bff22019-01-17 19:17:47 +0100252#define GPIO_BANK_J U(9)
253#define GPIO_BANK_K U(10)
254#define GPIO_BANK_Z U(25)
255
256#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100257#endif
Yann Gautier038bff22019-01-17 19:17:47 +0100258
259/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200260 * STM32MP1 UART
261 ******************************************************************************/
Yann Gautierd476c772022-07-05 13:29:13 +0200262#if STM32MP13
263#define USART1_BASE U(0x4C000000)
264#define USART2_BASE U(0x4C001000)
265#endif
266#if STM32MP15
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200267#define USART1_BASE U(0x5C000000)
268#define USART2_BASE U(0x4000E000)
Yann Gautierd476c772022-07-05 13:29:13 +0200269#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200270#define USART3_BASE U(0x4000F000)
271#define UART4_BASE U(0x40010000)
272#define UART5_BASE U(0x40011000)
273#define USART6_BASE U(0x44003000)
274#define UART7_BASE U(0x40018000)
275#define UART8_BASE U(0x40019000)
Yann Gautier038bff22019-01-17 19:17:47 +0100276
277/* For UART crash console */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100278#define STM32MP_DEBUG_USART_BASE UART4_BASE
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100279#if STM32MP13
280/* UART4 on HSI@64MHz, TX on GPIOF12 Alternate 8 (Disco board) */
281#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
282#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOD_BASE
283#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_S_AHB4ENSETR
284#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_S_AHB4ENSETR_GPIODEN
285#define DEBUG_UART_TX_GPIO_PORT 6
286#define DEBUG_UART_TX_GPIO_ALTERNATE 8
287#define DEBUG_UART_TX_CLKSRC_REG RCC_UART4CKSELR
288#define DEBUG_UART_TX_CLKSRC RCC_UART4CKSELR_HSI
289#endif /* STM32MP13 */
290#if STM32MP15
Yann Gautier038bff22019-01-17 19:17:47 +0100291/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100292#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
Yann Gautier038bff22019-01-17 19:17:47 +0100293#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
294#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
295#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
296#define DEBUG_UART_TX_GPIO_PORT 11
297#define DEBUG_UART_TX_GPIO_ALTERNATE 6
298#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
299#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100300#endif /* STM32MP15 */
Yann Gautier038bff22019-01-17 19:17:47 +0100301#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
302#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
Yann Gautier5c84e742020-09-14 17:21:59 +0200303#define DEBUG_UART_RST_REG RCC_APB1RSTSETR
304#define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200305
306/*******************************************************************************
Etienne Carrieree96162e2020-04-10 11:32:54 +0200307 * STM32MP1 ETZPC
308 ******************************************************************************/
309#define STM32MP1_ETZPC_BASE U(0x5C007000)
310
311/* ETZPC TZMA IDs */
312#define STM32MP1_ETZPC_TZMA_ROM U(0)
313#define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
314
315#define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
316
317/* ETZPC DECPROT IDs */
318#define STM32MP1_ETZPC_STGENC_ID 0
319#define STM32MP1_ETZPC_BKPSRAM_ID 1
320#define STM32MP1_ETZPC_IWDG1_ID 2
321#define STM32MP1_ETZPC_USART1_ID 3
322#define STM32MP1_ETZPC_SPI6_ID 4
323#define STM32MP1_ETZPC_I2C4_ID 5
324#define STM32MP1_ETZPC_RNG1_ID 7
325#define STM32MP1_ETZPC_HASH1_ID 8
326#define STM32MP1_ETZPC_CRYP1_ID 9
327#define STM32MP1_ETZPC_DDRCTRL_ID 10
328#define STM32MP1_ETZPC_DDRPHYC_ID 11
329#define STM32MP1_ETZPC_I2C6_ID 12
330#define STM32MP1_ETZPC_SEC_ID_LIMIT 13
331
332#define STM32MP1_ETZPC_TIM2_ID 16
333#define STM32MP1_ETZPC_TIM3_ID 17
334#define STM32MP1_ETZPC_TIM4_ID 18
335#define STM32MP1_ETZPC_TIM5_ID 19
336#define STM32MP1_ETZPC_TIM6_ID 20
337#define STM32MP1_ETZPC_TIM7_ID 21
338#define STM32MP1_ETZPC_TIM12_ID 22
339#define STM32MP1_ETZPC_TIM13_ID 23
340#define STM32MP1_ETZPC_TIM14_ID 24
341#define STM32MP1_ETZPC_LPTIM1_ID 25
342#define STM32MP1_ETZPC_WWDG1_ID 26
343#define STM32MP1_ETZPC_SPI2_ID 27
344#define STM32MP1_ETZPC_SPI3_ID 28
345#define STM32MP1_ETZPC_SPDIFRX_ID 29
346#define STM32MP1_ETZPC_USART2_ID 30
347#define STM32MP1_ETZPC_USART3_ID 31
348#define STM32MP1_ETZPC_UART4_ID 32
349#define STM32MP1_ETZPC_UART5_ID 33
350#define STM32MP1_ETZPC_I2C1_ID 34
351#define STM32MP1_ETZPC_I2C2_ID 35
352#define STM32MP1_ETZPC_I2C3_ID 36
353#define STM32MP1_ETZPC_I2C5_ID 37
354#define STM32MP1_ETZPC_CEC_ID 38
355#define STM32MP1_ETZPC_DAC_ID 39
356#define STM32MP1_ETZPC_UART7_ID 40
357#define STM32MP1_ETZPC_UART8_ID 41
358#define STM32MP1_ETZPC_MDIOS_ID 44
359#define STM32MP1_ETZPC_TIM1_ID 48
360#define STM32MP1_ETZPC_TIM8_ID 49
361#define STM32MP1_ETZPC_USART6_ID 51
362#define STM32MP1_ETZPC_SPI1_ID 52
363#define STM32MP1_ETZPC_SPI4_ID 53
364#define STM32MP1_ETZPC_TIM15_ID 54
365#define STM32MP1_ETZPC_TIM16_ID 55
366#define STM32MP1_ETZPC_TIM17_ID 56
367#define STM32MP1_ETZPC_SPI5_ID 57
368#define STM32MP1_ETZPC_SAI1_ID 58
369#define STM32MP1_ETZPC_SAI2_ID 59
370#define STM32MP1_ETZPC_SAI3_ID 60
371#define STM32MP1_ETZPC_DFSDM_ID 61
372#define STM32MP1_ETZPC_TT_FDCAN_ID 62
373#define STM32MP1_ETZPC_LPTIM2_ID 64
374#define STM32MP1_ETZPC_LPTIM3_ID 65
375#define STM32MP1_ETZPC_LPTIM4_ID 66
376#define STM32MP1_ETZPC_LPTIM5_ID 67
377#define STM32MP1_ETZPC_SAI4_ID 68
378#define STM32MP1_ETZPC_VREFBUF_ID 69
379#define STM32MP1_ETZPC_DCMI_ID 70
380#define STM32MP1_ETZPC_CRC2_ID 71
381#define STM32MP1_ETZPC_ADC_ID 72
382#define STM32MP1_ETZPC_HASH2_ID 73
383#define STM32MP1_ETZPC_RNG2_ID 74
384#define STM32MP1_ETZPC_CRYP2_ID 75
385#define STM32MP1_ETZPC_SRAM1_ID 80
386#define STM32MP1_ETZPC_SRAM2_ID 81
387#define STM32MP1_ETZPC_SRAM3_ID 82
388#define STM32MP1_ETZPC_SRAM4_ID 83
389#define STM32MP1_ETZPC_RETRAM_ID 84
390#define STM32MP1_ETZPC_OTG_ID 85
391#define STM32MP1_ETZPC_SDMMC3_ID 86
392#define STM32MP1_ETZPC_DLYBSD3_ID 87
393#define STM32MP1_ETZPC_DMA1_ID 88
394#define STM32MP1_ETZPC_DMA2_ID 89
395#define STM32MP1_ETZPC_DMAMUX_ID 90
396#define STM32MP1_ETZPC_FMC_ID 91
397#define STM32MP1_ETZPC_QSPI_ID 92
398#define STM32MP1_ETZPC_DLYBQ_ID 93
399#define STM32MP1_ETZPC_ETH_ID 94
400#define STM32MP1_ETZPC_RSV_ID 95
401
402#define STM32MP_ETZPC_MAX_ID 96
403
404/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200405 * STM32MP1 TZC (TZ400)
406 ******************************************************************************/
407#define STM32MP1_TZC_BASE U(0x5C006000)
408
Yann Gautier256c6b92020-10-21 18:15:12 +0200409#if STM32MP13
410#define STM32MP1_FILTER_BIT_ALL TZC_400_REGION_ATTR_FILTER_BIT(0)
411#endif
412#if STM32MP15
Yann Gautier2f974232020-09-17 12:25:05 +0200413#define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
414 TZC_400_REGION_ATTR_FILTER_BIT(1))
Yann Gautier256c6b92020-10-21 18:15:12 +0200415#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200416
417/*******************************************************************************
418 * STM32MP1 SDMMC
419 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +0100420#define STM32MP_SDMMC1_BASE U(0x58005000)
421#define STM32MP_SDMMC2_BASE U(0x58007000)
422#define STM32MP_SDMMC3_BASE U(0x48004000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200423
Yann Gautier4baf5822019-05-09 13:25:52 +0200424#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
425#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
426#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
427#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
428#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200429
430/*******************************************************************************
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100431 * STM32MP1 BSEC / OTP
432 ******************************************************************************/
433#define STM32MP1_OTP_MAX_ID 0x5FU
434#define STM32MP1_UPPER_OTP_START 0x20U
435
436#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
437
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100438/* OTP labels */
439#define CFG0_OTP "cfg0_otp"
440#define PART_NUMBER_OTP "part_number_otp"
Yann Gautier16188f32020-02-12 15:38:34 +0100441#if STM32MP15
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100442#define PACKAGE_OTP "package_otp"
Yann Gautier16188f32020-02-12 15:38:34 +0100443#endif
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100444#define HW2_OTP "hw2_otp"
Yann Gautierbde43da2021-08-18 15:03:40 +0200445#if STM32MP13
446#define NAND_OTP "cfg9_otp"
447#define NAND2_OTP "cfg10_otp"
448#endif
449#if STM32MP15
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100450#define NAND_OTP "nand_otp"
Yann Gautierbde43da2021-08-18 15:03:40 +0200451#endif
Yann Gautier5c1dab32019-04-17 15:12:58 +0200452#define MONOTONIC_OTP "monotonic_otp"
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100453#define UID_OTP "uid_otp"
454#define BOARD_ID_OTP "board_id"
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100455
456/* OTP mask */
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100457/* CFG0 */
Nicolas Le Bayon34cbf232020-11-26 09:57:09 +0100458#if STM32MP13
459#define CFG0_OTP_MODE_MASK GENMASK_32(9, 0)
460#define CFG0_OTP_MODE_SHIFT 0
461#define CFG0_OPEN_DEVICE 0x17U
462#define CFG0_CLOSED_DEVICE 0x3FU
463#define CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN 0x17FU
464#define CFG0_CLOSED_DEVICE_NO_JTAG 0x3FFU
465#endif
466#if STM32MP15
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100467#define CFG0_CLOSED_DEVICE BIT(6)
Nicolas Le Bayon34cbf232020-11-26 09:57:09 +0100468#endif
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100469
Yann Gautierc7374052019-06-04 18:02:37 +0200470/* PART NUMBER */
Yann Gautier16188f32020-02-12 15:38:34 +0100471#if STM32MP13
472#define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0)
473#endif
474#if STM32MP15
Yann Gautierc7374052019-06-04 18:02:37 +0200475#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
Yann Gautier16188f32020-02-12 15:38:34 +0100476#endif
Yann Gautierc7374052019-06-04 18:02:37 +0200477#define PART_NUMBER_OTP_PART_SHIFT 0
478
479/* PACKAGE */
Yann Gautier16188f32020-02-12 15:38:34 +0100480#if STM32MP15
Yann Gautierc7374052019-06-04 18:02:37 +0200481#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
482#define PACKAGE_OTP_PKG_SHIFT 27
Yann Gautier16188f32020-02-12 15:38:34 +0100483#endif
Yann Gautierc7374052019-06-04 18:02:37 +0200484
Yann Gautier091eab52019-06-04 18:06:34 +0200485/* IWDG OTP */
486#define HW2_OTP_IWDG_HW_POS U(3)
487#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
488#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
489
Yann Gautier3edc7c32019-05-20 19:17:08 +0200490/* HW2 OTP */
491#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
492
Lionel Debieve402a46b2019-11-04 12:28:15 +0100493/* NAND OTP */
494/* NAND parameter storage flag */
495#define NAND_PARAM_STORED_IN_OTP BIT(31)
496
497/* NAND page size in bytes */
498#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
499#define NAND_PAGE_SIZE_SHIFT 29
500#define NAND_PAGE_SIZE_2K U(0)
501#define NAND_PAGE_SIZE_4K U(1)
502#define NAND_PAGE_SIZE_8K U(2)
503
504/* NAND block size in pages */
505#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
506#define NAND_BLOCK_SIZE_SHIFT 27
507#define NAND_BLOCK_SIZE_64_PAGES U(0)
508#define NAND_BLOCK_SIZE_128_PAGES U(1)
509#define NAND_BLOCK_SIZE_256_PAGES U(2)
510
Yann Gautierbde43da2021-08-18 15:03:40 +0200511/* NAND number of block (in unit of 256 blocks) */
Lionel Debieve402a46b2019-11-04 12:28:15 +0100512#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
513#define NAND_BLOCK_NB_SHIFT 19
514#define NAND_BLOCK_NB_UNIT U(256)
515
516/* NAND bus width in bits */
517#define NAND_WIDTH_MASK BIT(18)
518#define NAND_WIDTH_SHIFT 18
519
520/* NAND number of ECC bits per 512 bytes */
521#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
522#define NAND_ECC_BIT_NB_SHIFT 15
523#define NAND_ECC_BIT_NB_UNSET U(0)
524#define NAND_ECC_BIT_NB_1_BITS U(1)
525#define NAND_ECC_BIT_NB_4_BITS U(2)
526#define NAND_ECC_BIT_NB_8_BITS U(3)
527#define NAND_ECC_ON_DIE U(4)
528
Lionel Debieve186b0462019-09-24 18:30:12 +0200529/* NAND number of planes */
530#define NAND_PLANE_BIT_NB_MASK BIT(14)
531
Yann Gautierbde43da2021-08-18 15:03:40 +0200532/* NAND2 OTP */
533#define NAND2_PAGE_SIZE_SHIFT 16
534
535/* NAND2 config distribution */
536#define NAND2_CONFIG_DISTRIB BIT(0)
537#define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
538#define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
539
Yann Gautier5c1dab32019-04-17 15:12:58 +0200540/* MONOTONIC OTP */
541#define MAX_MONOTONIC_VALUE 32
542
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200543/* UID OTP */
544#define UID_WORD_NB U(3)
545
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100546/* FWU configuration (max supported value is 15) */
547#define FWU_MAX_TRIAL_REBOOT U(3)
548
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100549/*******************************************************************************
Yann Gautier41934662018-07-20 11:36:05 +0200550 * STM32MP1 TAMP
551 ******************************************************************************/
552#define TAMP_BASE U(0x5C00A000)
553#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
554
Julius Werner53456fc2019-07-09 13:49:11 -0700555#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
Nicolas Toromanoffbb82b1b2022-02-09 12:26:31 +0100556static inline uintptr_t tamp_bkpr(uint32_t idx)
Yann Gautier41934662018-07-20 11:36:05 +0200557{
558 return TAMP_BKP_REGISTER_BASE + (idx << 2);
559}
560#endif
561
562/*******************************************************************************
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200563 * STM32MP1 USB
564 ******************************************************************************/
565#define USB_OTG_BASE U(0x49000000)
566
567/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200568 * STM32MP1 DDRCTRL
569 ******************************************************************************/
570#define DDRCTRL_BASE U(0x5A003000)
571
572/*******************************************************************************
573 * STM32MP1 DDRPHYC
574 ******************************************************************************/
575#define DDRPHYC_BASE U(0x5A004000)
576
577/*******************************************************************************
Yann Gautier091eab52019-06-04 18:06:34 +0200578 * STM32MP1 IWDG
579 ******************************************************************************/
580#define IWDG_MAX_INSTANCE U(2)
581#define IWDG1_INST U(0)
582#define IWDG2_INST U(1)
583
584#define IWDG1_BASE U(0x5C003000)
585#define IWDG2_BASE U(0x5A002000)
586
587/*******************************************************************************
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200588 * Miscellaneous STM32MP1 peripherals base address
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200589 ******************************************************************************/
Yann Gautiera18f61b2020-05-05 17:58:40 +0200590#define BSEC_BASE U(0x5C005000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100591#if STM32MP13
592#define CRYP_BASE U(0x54002000)
593#endif
594#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200595#define CRYP1_BASE U(0x54001000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100596#endif
Yann Gautier091eab52019-06-04 18:06:34 +0200597#define DBGMCU_BASE U(0x50081000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100598#if STM32MP13
599#define HASH_BASE U(0x54003000)
600#endif
601#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200602#define HASH1_BASE U(0x54002000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100603#endif
604#if STM32MP13
605#define I2C3_BASE U(0x4C004000)
606#define I2C4_BASE U(0x4C005000)
607#define I2C5_BASE U(0x4C006000)
608#endif
609#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200610#define I2C4_BASE U(0x5C002000)
611#define I2C6_BASE U(0x5c009000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100612#endif
613#if STM32MP13
614#define RNG_BASE U(0x54004000)
615#endif
616#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200617#define RNG1_BASE U(0x54003000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100618#endif
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200619#define RTC_BASE U(0x5c004000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100620#if STM32MP13
621#define SPI4_BASE U(0x4C002000)
622#define SPI5_BASE U(0x4C003000)
623#endif
624#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200625#define SPI6_BASE U(0x5c001000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100626#endif
Yann Gautiera18f61b2020-05-05 17:58:40 +0200627#define STGEN_BASE U(0x5c008000)
628#define SYSCFG_BASE U(0x50020000)
Yann Gautier091eab52019-06-04 18:06:34 +0200629
630/*******************************************************************************
Yann Gautier434fa2d2021-03-23 15:25:04 +0100631 * STM32MP13 SAES
632 ******************************************************************************/
633#define SAES_BASE U(0x54005000)
634
635/*******************************************************************************
636 * STM32MP13 PKA
637 ******************************************************************************/
638#define PKA_BASE U(0x54006000)
639
640/*******************************************************************************
Yann Gautierb1279e72021-12-15 13:16:15 +0100641 * REGULATORS
642 ******************************************************************************/
643/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
644#define PLAT_NB_RDEVS U(19)
Lionel Debieve84cbde32021-04-15 08:27:28 +0200645/* 2 FIXED */
646#define PLAT_NB_FIXED_REGS U(2)
Yann Gautierb1279e72021-12-15 13:16:15 +0100647
648/*******************************************************************************
Yann Gautier4d429472019-02-14 11:15:20 +0100649 * Device Tree defines
650 ******************************************************************************/
Yann Gautier35dc0772019-05-13 18:34:48 +0200651#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
Nicolas Le Bayon01087912021-01-12 18:18:27 +0100652#if STM32MP13
653#define DT_DDR_COMPAT "st,stm32mp13-ddr"
654#endif
655#if STM32MP15
Nicolas Le Bayon8ce825f2021-05-18 10:01:30 +0200656#define DT_DDR_COMPAT "st,stm32mp1-ddr"
Nicolas Le Bayon01087912021-01-12 18:18:27 +0100657#endif
Yann Gautier091eab52019-06-04 18:06:34 +0200658#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
Yann Gautier4ede20a2020-09-18 15:04:14 +0200659#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100660#if STM32MP13
661#define DT_RCC_CLK_COMPAT "st,stm32mp13-rcc"
662#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp13-rcc-secure"
663#endif
664#if STM32MP15
Yann Gautier4d429472019-02-14 11:15:20 +0100665#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
Lionel Debieve3c0fbfe2020-12-15 10:35:59 +0100666#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure"
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100667#endif
Yann Gautier006bb512021-01-20 14:10:57 +0100668#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
Yann Gautier4d429472019-02-14 11:15:20 +0100669
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200670#endif /* STM32MP1_DEF_H */