blob: 890433983546e234214d12199f5e91fe11b1603f [file] [log] [blame]
Oliver Swede8fed2fe2019-11-11 11:11:06 +00001#
2# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Andre Przywaraeec45eb2020-01-24 15:02:27 +00007include lib/libfdt/libfdt.mk
8
Oliver Swede8fed2fe2019-11-11 11:11:06 +00009RESET_TO_BL31 := 1
10ifeq (${RESET_TO_BL31}, 0)
11$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
12endif
13
Oliver Swede3769b3f2019-12-16 14:08:27 +000014ifeq (${ENABLE_PIE}, 1)
15override SEPARATE_CODE_AND_RODATA := 1
16endif
17
Oliver Swede8fed2fe2019-11-11 11:11:06 +000018CTX_INCLUDE_AARCH32_REGS := 0
19ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
20$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
21endif
22
23ifeq (${TRUSTED_BOARD_BOOT}, 1)
24$(error "TRUSTED_BOARD_BOOT must be disabled")
25endif
26
Andre Przywarad9b95cc2020-07-08 13:01:00 +010027PRELOADED_BL33_BASE := 0x80080000
Oliver Swede8fed2fe2019-11-11 11:11:06 +000028
Andre Przywarad9b95cc2020-07-08 13:01:00 +010029FPGA_PRELOADED_DTB_BASE := 0x80070000
Oliver Swede8fed2fe2019-11-11 11:11:06 +000030$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
Oliver Swede8fed2fe2019-11-11 11:11:06 +000031
Andre Przywara01767932020-07-07 10:40:46 +010032FPGA_PRELOADED_CMD_LINE := 0x1000
33$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE))
34
Oliver Swede8fed2fe2019-11-11 11:11:06 +000035# Treating this as a memory-constrained port for now
36USE_COHERENT_MEM := 0
37
Oliver Swede7fbb9b52020-01-15 10:20:09 +000038# This can be overridden depending on CPU(s) used in the FPGA image
Oliver Swede8fed2fe2019-11-11 11:11:06 +000039HW_ASSISTED_COHERENCY := 1
40
Andre Przywara8b505252020-04-09 10:10:09 +010041PL011_GENERIC_UART := 1
42
Oliver Swede7fbb9b52020-01-15 10:20:09 +000043FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
44
45# select a different set of CPU files, depending on whether we compile for
46# hardware assisted coherency cores or not
47ifeq (${HW_ASSISTED_COHERENCY}, 0)
48# Cores used without DSU
49 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
50 lib/cpus/aarch64/cortex_a53.S \
51 lib/cpus/aarch64/cortex_a57.S \
52 lib/cpus/aarch64/cortex_a72.S \
53 lib/cpus/aarch64/cortex_a73.S
54else
55# AArch64-only cores
56 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
57 lib/cpus/aarch64/cortex_a76ae.S \
58 lib/cpus/aarch64/cortex_a77.S \
Jimmy Brisson7ec175e2020-06-01 16:49:34 -050059 lib/cpus/aarch64/cortex_a78.S \
Oliver Swede7fbb9b52020-01-15 10:20:09 +000060 lib/cpus/aarch64/neoverse_n1.S \
61 lib/cpus/aarch64/neoverse_e1.S \
62 lib/cpus/aarch64/neoverse_zeus.S \
Oliver Swede7fbb9b52020-01-15 10:20:09 +000063 lib/cpus/aarch64/cortex_hercules_ae.S \
64 lib/cpus/aarch64/cortex_a65.S \
Andre Przywaracb167672020-06-25 13:10:38 +010065 lib/cpus/aarch64/cortex_a65ae.S \
66 lib/cpus/aarch64/cortex_klein.S \
67 lib/cpus/aarch64/cortex_matterhorn.S
68
Oliver Swede7fbb9b52020-01-15 10:20:09 +000069# AArch64/AArch32 cores
70 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
71 lib/cpus/aarch64/cortex_a75.S
72endif
Oliver Swede8fed2fe2019-11-11 11:11:06 +000073
Andre Przywarae1cc1302020-03-25 15:50:38 +000074# Allow detection of GIC-600
75GICV3_SUPPORT_GIC600 := 1
Manish Pandeyb21cad72020-04-03 18:59:20 +010076
77# Include GICv3 driver files
78include drivers/arm/gic/v3/gicv3.mk
79
80FPGA_GIC_SOURCES := ${GICV3_SOURCES} \
Oliver Swedeb51da812019-12-03 14:08:21 +000081 plat/common/plat_gicv3.c \
82 plat/arm/board/arm_fpga/fpga_gicv3.c
Oliver Swede8fed2fe2019-11-11 11:11:06 +000083
84PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
85
86PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
87
Andre Przywaraeec45eb2020-01-24 15:02:27 +000088BL31_SOURCES += common/fdt_wrappers.c \
Javier Almansa Sobrino3bcf3c82020-06-04 19:01:48 +010089 common/fdt_fixup.c \
Andre Przywaraeec45eb2020-01-24 15:02:27 +000090 drivers/delay_timer/delay_timer.c \
Oliver Swede8fed2fe2019-11-11 11:11:06 +000091 drivers/delay_timer/generic_delay_timer.c \
92 drivers/arm/pl011/${ARCH}/pl011_console.S \
93 plat/common/plat_psci_common.c \
94 plat/arm/board/arm_fpga/fpga_pm.c \
95 plat/arm/board/arm_fpga/fpga_topology.c \
96 plat/arm/board/arm_fpga/fpga_console.c \
97 plat/arm/board/arm_fpga/fpga_bl31_setup.c \
98 ${FPGA_CPU_LIBS} \
99 ${FPGA_GIC_SOURCES}
100
101all: bl31