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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +01002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +010032#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <context.h>
dp-arm3cac7862016-09-19 11:18:44 +010034#include <cpu_data.h>
Achin Gupta9cf2bb72014-05-09 11:07:09 +010035#include <interrupt_mgmt.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010036#include <platform_def.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010037#include <runtime_svc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010038
39 .globl runtime_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
Douglas Raillard0980eed2016-11-09 17:48:27 +000041 /* ---------------------------------------------------------------------
42 * This macro handles Synchronous exceptions.
43 * Only SMC exceptions are supported.
44 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +010045 */
46 .macro handle_sync_exception
Achin Guptaed1744e2014-08-04 23:13:10 +010047 /* Enable the SError interrupt */
48 msr daifclr, #DAIF_ABT_BIT
49
Achin Gupta9cf2bb72014-05-09 11:07:09 +010050 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
dp-arm3cac7862016-09-19 11:18:44 +010051
52#if ENABLE_RUNTIME_INSTRUMENTATION
dp-arm3cac7862016-09-19 11:18:44 +010053 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +000054 * Read the timestamp value and store it in per-cpu data. The value
55 * will be extracted from per-cpu data by the C level SMC handler and
56 * saved to the PMF timestamp region.
dp-arm3cac7862016-09-19 11:18:44 +010057 */
58 mrs x30, cntpct_el0
59 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
60 mrs x29, tpidr_el3
61 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
62 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
63#endif
64
Achin Gupta9cf2bb72014-05-09 11:07:09 +010065 mrs x30, esr_el3
66 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
67
Douglas Raillard0980eed2016-11-09 17:48:27 +000068 /* Handle SMC exceptions separately from other synchronous exceptions */
Achin Gupta9cf2bb72014-05-09 11:07:09 +010069 cmp x30, #EC_AARCH32_SMC
70 b.eq smc_handler32
71
72 cmp x30, #EC_AARCH64_SMC
73 b.eq smc_handler64
74
Douglas Raillard0980eed2016-11-09 17:48:27 +000075 /* Other kinds of synchronous exceptions are not handled */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000076 no_ret report_unhandled_exception
Achin Gupta9cf2bb72014-05-09 11:07:09 +010077 .endm
78
79
Douglas Raillard0980eed2016-11-09 17:48:27 +000080 /* ---------------------------------------------------------------------
81 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
82 * interrupts.
83 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +010084 */
85 .macro handle_interrupt_exception label
Achin Guptaed1744e2014-08-04 23:13:10 +010086 /* Enable the SError interrupt */
87 msr daifclr, #DAIF_ABT_BIT
88
Achin Gupta9cf2bb72014-05-09 11:07:09 +010089 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
90 bl save_gp_registers
91
Douglas Raillard0980eed2016-11-09 17:48:27 +000092 /* Save the EL3 system registers needed to return from this exception */
Achin Gupta979992e2015-05-13 17:57:18 +010093 mrs x0, spsr_el3
94 mrs x1, elr_el3
95 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
96
Achin Gupta9cf2bb72014-05-09 11:07:09 +010097 /* Switch to the runtime stack i.e. SP_EL0 */
98 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
99 mov x20, sp
100 msr spsel, #0
101 mov sp, x2
102
103 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000104 * Find out whether this is a valid interrupt type.
105 * If the interrupt controller reports a spurious interrupt then return
106 * to where we came from.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100107 */
Dan Handley701fea72014-05-27 16:17:21 +0100108 bl plat_ic_get_pending_interrupt_type
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100109 cmp x0, #INTR_TYPE_INVAL
110 b.eq interrupt_exit_\label
111
112 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000113 * Get the registered handler for this interrupt type.
114 * A NULL return value could be 'cause of the following conditions:
Achin Gupta979992e2015-05-13 17:57:18 +0100115 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000116 * a. An interrupt of a type was routed correctly but a handler for its
117 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100118 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000119 * b. An interrupt of a type was not routed correctly so a handler for
120 * its type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100121 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000122 * c. An interrupt of a type was routed correctly to EL3, but was
123 * deasserted before its pending state could be read. Another
124 * interrupt of a different type pended at the same time and its
125 * type was reported as pending instead. However, a handler for this
126 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100127 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000128 * a. and b. can only happen due to a programming error. The
129 * occurrence of c. could be beyond the control of Trusted Firmware.
130 * It makes sense to return from this exception instead of reporting an
131 * error.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100132 */
133 bl get_interrupt_type_handler
Achin Gupta979992e2015-05-13 17:57:18 +0100134 cbz x0, interrupt_exit_\label
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100135 mov x21, x0
136
137 mov x0, #INTR_ID_UNAVAILABLE
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100138
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100139 /* Set the current security state in the 'flags' parameter */
140 mrs x2, scr_el3
141 ubfx x1, x2, #0, #1
142
143 /* Restore the reference to the 'handle' i.e. SP_EL3 */
144 mov x2, x20
145
Douglas Raillard0980eed2016-11-09 17:48:27 +0000146 /* x3 will point to a cookie (not used now) */
Soby Mathew799f0ab2014-05-27 16:54:31 +0100147 mov x3, xzr
148
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100149 /* Call the interrupt type handler */
150 blr x21
151
152interrupt_exit_\label:
153 /* Return from exception, possibly in a different security state */
154 b el3_exit
155
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100156 .endm
157
158
Soby Mathew6c5192a2014-04-30 15:36:37 +0100159 .macro save_x18_to_x29_sp_el0
160 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
161 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
162 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
163 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
164 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
165 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
166 mrs x18, sp_el0
167 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
168 .endm
169
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100170
171vector_base runtime_exceptions
172
Douglas Raillard0980eed2016-11-09 17:48:27 +0000173 /* ---------------------------------------------------------------------
174 * Current EL with SP_EL0 : 0x0 - 0x200
175 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100176 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100177vector_entry sync_exception_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000178 /* We don't expect any synchronous exceptions from EL3 */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000179 no_ret report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000180 check_vector_size sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100182vector_entry irq_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000183 /*
184 * EL3 code is non-reentrant. Any asynchronous exception is a serious
185 * error. Loop infinitely.
186 */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000187 no_ret report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000188 check_vector_size irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100189
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100190
191vector_entry fiq_sp_el0
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000192 no_ret report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000193 check_vector_size fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100194
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100195
196vector_entry serror_sp_el0
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000197 no_ret report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000198 check_vector_size serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100199
Douglas Raillard0980eed2016-11-09 17:48:27 +0000200 /* ---------------------------------------------------------------------
201 * Current EL with SP_ELx: 0x200 - 0x400
202 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100204vector_entry sync_exception_sp_elx
Douglas Raillard0980eed2016-11-09 17:48:27 +0000205 /*
206 * This exception will trigger if anything went wrong during a previous
207 * exception entry or exit or while handling an earlier unexpected
208 * synchronous exception. There is a high probability that SP_EL3 is
209 * corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000210 */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000211 no_ret report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000212 check_vector_size sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100213
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100214vector_entry irq_sp_elx
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000215 no_ret report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000216 check_vector_size irq_sp_elx
217
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100218vector_entry fiq_sp_elx
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000219 no_ret report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000220 check_vector_size fiq_sp_elx
221
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100222vector_entry serror_sp_elx
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000223 no_ret report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000224 check_vector_size serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225
Douglas Raillard0980eed2016-11-09 17:48:27 +0000226 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100227 * Lower EL using AArch64 : 0x400 - 0x600
Douglas Raillard0980eed2016-11-09 17:48:27 +0000228 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100230vector_entry sync_exception_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000231 /*
232 * This exception vector will be the entry point for SMCs and traps
233 * that are unhandled at lower ELs most commonly. SP_EL3 should point
234 * to a valid cpu context where the general purpose and system register
235 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000236 */
237 handle_sync_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000238 check_vector_size sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100239
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100240vector_entry irq_aarch64
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100241 handle_interrupt_exception irq_aarch64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000242 check_vector_size irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100244vector_entry fiq_aarch64
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100245 handle_interrupt_exception fiq_aarch64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000246 check_vector_size fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100247
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100248vector_entry serror_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000249 /*
250 * SError exceptions from lower ELs are not currently supported.
251 * Report their occurrence.
252 */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000253 no_ret report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000254 check_vector_size serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100255
Douglas Raillard0980eed2016-11-09 17:48:27 +0000256 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100257 * Lower EL using AArch32 : 0x600 - 0x800
Douglas Raillard0980eed2016-11-09 17:48:27 +0000258 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100259 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100260vector_entry sync_exception_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000261 /*
262 * This exception vector will be the entry point for SMCs and traps
263 * that are unhandled at lower ELs most commonly. SP_EL3 should point
264 * to a valid cpu context where the general purpose and system register
265 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000266 */
267 handle_sync_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000268 check_vector_size sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100269
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100270vector_entry irq_aarch32
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100271 handle_interrupt_exception irq_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000272 check_vector_size irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100273
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100274vector_entry fiq_aarch32
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100275 handle_interrupt_exception fiq_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000276 check_vector_size fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100278vector_entry serror_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000279 /*
280 * SError exceptions from lower ELs are not currently supported.
281 * Report their occurrence.
282 */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000283 no_ret report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000284 check_vector_size serror_aarch32
285
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000286
Douglas Raillard0980eed2016-11-09 17:48:27 +0000287 /* ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000288 * The following code handles secure monitor calls.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000289 * Depending upon the execution state from where the SMC has been
290 * invoked, it frees some general purpose registers to perform the
291 * remaining tasks. They involve finding the runtime service handler
292 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
293 * before calling the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000294 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000295 * Note that x30 has been explicitly saved and can be used here
296 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000297 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000298func smc_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000299smc_handler32:
300 /* Check whether aarch32 issued an SMC64 */
301 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
302
Douglas Raillard0980eed2016-11-09 17:48:27 +0000303 /*
304 * Since we're are coming from aarch32, x8-x18 need to be saved as per
305 * SMC32 calling convention. If a lower EL in aarch64 is making an
306 * SMC32 call then it must have saved x8-x17 already therein.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000307 */
308 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
309 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
310 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
311 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
312 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
313
314 /* x4-x7, x18, sp_el0 are saved below */
315
316smc_handler64:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000317 /*
318 * Populate the parameters for the SMC handler.
319 * We already have x0-x4 in place. x5 will point to a cookie (not used
320 * now). x6 will point to the context structure (SP_EL3) and x7 will
321 * contain flags we need to pass to the handler Hence save x5-x7.
322 *
323 * Note: x4 only needs to be preserved for AArch32 callers but we do it
324 * for AArch64 callers as well for convenience
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000325 */
326 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
327 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
328
Soby Mathew6c5192a2014-04-30 15:36:37 +0100329 /* Save rest of the gpregs and sp_el0*/
330 save_x18_to_x29_sp_el0
331
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000332 mov x5, xzr
333 mov x6, sp
334
335 /* Get the unique owning entity number */
336 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
337 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
338 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
339
340 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
341
342 /* Load descriptor index from array of indices */
343 adr x14, rt_svc_descs_indices
344 ldrb w15, [x14, x16]
345
Douglas Raillard0980eed2016-11-09 17:48:27 +0000346 /*
347 * Restore the saved C runtime stack value which will become the new
348 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
349 * structure prior to the last ERET from EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000350 */
351 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
352
353 /*
354 * Any index greater than 127 is invalid. Check bit 7 for
355 * a valid index
356 */
357 tbnz w15, 7, smc_unknown
358
359 /* Switch to SP_EL0 */
360 msr spsel, #0
361
Douglas Raillard0980eed2016-11-09 17:48:27 +0000362 /*
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000363 * Get the descriptor using the index
364 * x11 = (base + off), x15 = index
365 *
366 * handler = (base + off) + (index << log2(size))
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000367 */
368 lsl w10, w15, #RT_SVC_SIZE_LOG2
369 ldr x15, [x11, w10, uxtw]
370
Douglas Raillard0980eed2016-11-09 17:48:27 +0000371 /*
372 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
373 * switch during SMC handling.
374 * TODO: Revisit if all system registers can be saved later.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000375 */
376 mrs x16, spsr_el3
377 mrs x17, elr_el3
378 mrs x18, scr_el3
379 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Achin Guptae1aa5162014-06-26 09:58:52 +0100380 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000381
382 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
383 bfi x7, x18, #0, #1
384
385 mov sp, x12
386
Douglas Raillard0980eed2016-11-09 17:48:27 +0000387 /*
388 * Call the Secure Monitor Call handler and then drop directly into
389 * el3_exit() which will program any remaining architectural state
390 * prior to issuing the ERET to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000391 */
392#if DEBUG
393 cbz x15, rt_svc_fw_critical_error
394#endif
395 blr x15
396
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100397 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100398
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000399smc_unknown:
400 /*
401 * Here we restore x4-x18 regardless of where we came from. AArch32
402 * callers will find the registers contents unchanged, but AArch64
403 * callers will find the registers modified (with stale earlier NS
404 * content). Either way, we aren't leaking any secure information
Douglas Raillard0980eed2016-11-09 17:48:27 +0000405 * through them.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000406 */
Soby Mathew5e5c2072014-04-07 15:28:55 +0100407 mov w0, #SMC_UNK
408 b restore_gp_registers_callee_eret
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000409
410smc_prohibited:
Soby Mathew6c5192a2014-04-30 15:36:37 +0100411 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000412 mov w0, #SMC_UNK
413 eret
414
415rt_svc_fw_critical_error:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000416 /* Switch to SP_ELx */
417 msr spsel, #1
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000418 no_ret report_unhandled_exception
Kévin Petita877c252015-03-24 14:03:57 +0000419endfunc smc_handler