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Yann Gautier9aea69e2018-07-24 17:13:36 +02001/*
Yann Gautiera2e2a302019-02-14 11:13:39 +01002 * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
Yann Gautier9aea69e2018-07-24 17:13:36 +02003 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
Yann Gautier9aea69e2018-07-24 17:13:36 +02007#include <assert.h>
Yann Gautier9aea69e2018-07-24 17:13:36 +02008#include <errno.h>
Yann Gautier9aea69e2018-07-24 17:13:36 +02009#include <stdint.h>
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010010#include <stdio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <libfdt.h>
13
Yann Gautier57e282b2019-01-07 11:17:24 +010014#include <platform_def.h>
15
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <arch.h>
17#include <arch_helpers.h>
18#include <common/debug.h>
Andre Przywaracc99f3f2020-03-26 12:51:21 +000019#include <common/fdt_wrappers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <drivers/delay_timer.h>
21#include <drivers/generic_delay_timer.h>
Yann Gautier4d429472019-02-14 11:15:20 +010022#include <drivers/st/stm32mp_clkfunc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <drivers/st/stm32mp1_clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <drivers/st/stm32mp1_rcc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000025#include <dt-bindings/clock/stm32mp1-clksrc.h>
26#include <lib/mmio.h>
Yann Gautiere4a3c352019-02-14 10:53:33 +010027#include <lib/spinlock.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000028#include <lib/utils_def.h>
29#include <plat/common/platform.h>
30
Yann Gautier2299d572019-02-14 11:14:39 +010031#define MAX_HSI_HZ 64000000
Yann Gautiere4a3c352019-02-14 10:53:33 +010032#define USB_PHY_48_MHZ 48000000
Yann Gautier9aea69e2018-07-24 17:13:36 +020033
Yann Gautier2299d572019-02-14 11:14:39 +010034#define TIMEOUT_US_200MS U(200000)
35#define TIMEOUT_US_1S U(1000000)
Yann Gautier9aea69e2018-07-24 17:13:36 +020036
Yann Gautier2299d572019-02-14 11:14:39 +010037#define PLLRDY_TIMEOUT TIMEOUT_US_200MS
38#define CLKSRC_TIMEOUT TIMEOUT_US_200MS
39#define CLKDIV_TIMEOUT TIMEOUT_US_200MS
40#define HSIDIV_TIMEOUT TIMEOUT_US_200MS
41#define OSCRDY_TIMEOUT TIMEOUT_US_1S
Yann Gautier9aea69e2018-07-24 17:13:36 +020042
Yann Gautier5f2e8742019-05-17 15:57:56 +020043const char *stm32mp_osc_node_label[NB_OSC] = {
44 [_LSI] = "clk-lsi",
45 [_LSE] = "clk-lse",
46 [_HSI] = "clk-hsi",
47 [_HSE] = "clk-hse",
48 [_CSI] = "clk-csi",
49 [_I2S_CKIN] = "i2s_ckin",
50};
51
Yann Gautier9aea69e2018-07-24 17:13:36 +020052enum stm32mp1_parent_id {
53/* Oscillators are defined in enum stm32mp_osc_id */
54
55/* Other parent source */
56 _HSI_KER = NB_OSC,
57 _HSE_KER,
58 _HSE_KER_DIV2,
59 _CSI_KER,
60 _PLL1_P,
61 _PLL1_Q,
62 _PLL1_R,
63 _PLL2_P,
64 _PLL2_Q,
65 _PLL2_R,
66 _PLL3_P,
67 _PLL3_Q,
68 _PLL3_R,
69 _PLL4_P,
70 _PLL4_Q,
71 _PLL4_R,
72 _ACLK,
73 _PCLK1,
74 _PCLK2,
75 _PCLK3,
76 _PCLK4,
77 _PCLK5,
78 _HCLK6,
79 _HCLK2,
80 _CK_PER,
81 _CK_MPU,
Yann Gautiered342322019-02-15 17:33:27 +010082 _CK_MCU,
Yann Gautiere4a3c352019-02-14 10:53:33 +010083 _USB_PHY_48,
Yann Gautier9aea69e2018-07-24 17:13:36 +020084 _PARENT_NB,
85 _UNKNOWN_ID = 0xff,
86};
87
Yann Gautiere4a3c352019-02-14 10:53:33 +010088/* Lists only the parent clock we are interested in */
Yann Gautier9aea69e2018-07-24 17:13:36 +020089enum stm32mp1_parent_sel {
Yann Gautiere4a3c352019-02-14 10:53:33 +010090 _I2C12_SEL,
91 _I2C35_SEL,
92 _STGEN_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +020093 _I2C46_SEL,
Yann Gautiere4a3c352019-02-14 10:53:33 +010094 _SPI6_SEL,
Yann Gautier9d8bbcd2019-05-07 18:49:33 +020095 _UART1_SEL,
Yann Gautiere4a3c352019-02-14 10:53:33 +010096 _RNG1_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +020097 _UART6_SEL,
98 _UART24_SEL,
99 _UART35_SEL,
100 _UART78_SEL,
101 _SDMMC12_SEL,
102 _SDMMC3_SEL,
103 _QSPI_SEL,
104 _FMC_SEL,
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200105 _AXIS_SEL,
106 _MCUS_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200107 _USBPHY_SEL,
108 _USBO_SEL,
Etienne Carriere04132612019-12-08 08:20:12 +0100109 _MPU_SEL,
110 _PER_SEL,
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100111 _RTC_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200112 _PARENT_SEL_NB,
113 _UNKNOWN_SEL = 0xff,
114};
115
Etienne Carriere04132612019-12-08 08:20:12 +0100116/* State the parent clock ID straight related to a clock */
117static const uint8_t parent_id_clock_id[_PARENT_NB] = {
118 [_HSE] = CK_HSE,
119 [_HSI] = CK_HSI,
120 [_CSI] = CK_CSI,
121 [_LSE] = CK_LSE,
122 [_LSI] = CK_LSI,
123 [_I2S_CKIN] = _UNKNOWN_ID,
124 [_USB_PHY_48] = _UNKNOWN_ID,
125 [_HSI_KER] = CK_HSI,
126 [_HSE_KER] = CK_HSE,
127 [_HSE_KER_DIV2] = CK_HSE_DIV2,
128 [_CSI_KER] = CK_CSI,
129 [_PLL1_P] = PLL1_P,
130 [_PLL1_Q] = PLL1_Q,
131 [_PLL1_R] = PLL1_R,
132 [_PLL2_P] = PLL2_P,
133 [_PLL2_Q] = PLL2_Q,
134 [_PLL2_R] = PLL2_R,
135 [_PLL3_P] = PLL3_P,
136 [_PLL3_Q] = PLL3_Q,
137 [_PLL3_R] = PLL3_R,
138 [_PLL4_P] = PLL4_P,
139 [_PLL4_Q] = PLL4_Q,
140 [_PLL4_R] = PLL4_R,
141 [_ACLK] = CK_AXI,
142 [_PCLK1] = CK_AXI,
143 [_PCLK2] = CK_AXI,
144 [_PCLK3] = CK_AXI,
145 [_PCLK4] = CK_AXI,
146 [_PCLK5] = CK_AXI,
147 [_CK_PER] = CK_PER,
148 [_CK_MPU] = CK_MPU,
149 [_CK_MCU] = CK_MCU,
150};
151
152static unsigned int clock_id2parent_id(unsigned long id)
153{
154 unsigned int n;
155
156 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) {
157 if (parent_id_clock_id[n] == id) {
158 return n;
159 }
160 }
161
162 return _UNKNOWN_ID;
163}
164
Yann Gautier9aea69e2018-07-24 17:13:36 +0200165enum stm32mp1_pll_id {
166 _PLL1,
167 _PLL2,
168 _PLL3,
169 _PLL4,
170 _PLL_NB
171};
172
173enum stm32mp1_div_id {
174 _DIV_P,
175 _DIV_Q,
176 _DIV_R,
177 _DIV_NB,
178};
179
180enum stm32mp1_clksrc_id {
181 CLKSRC_MPU,
182 CLKSRC_AXI,
Yann Gautiered342322019-02-15 17:33:27 +0100183 CLKSRC_MCU,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200184 CLKSRC_PLL12,
185 CLKSRC_PLL3,
186 CLKSRC_PLL4,
187 CLKSRC_RTC,
188 CLKSRC_MCO1,
189 CLKSRC_MCO2,
190 CLKSRC_NB
191};
192
193enum stm32mp1_clkdiv_id {
194 CLKDIV_MPU,
195 CLKDIV_AXI,
Yann Gautiered342322019-02-15 17:33:27 +0100196 CLKDIV_MCU,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200197 CLKDIV_APB1,
198 CLKDIV_APB2,
199 CLKDIV_APB3,
200 CLKDIV_APB4,
201 CLKDIV_APB5,
202 CLKDIV_RTC,
203 CLKDIV_MCO1,
204 CLKDIV_MCO2,
205 CLKDIV_NB
206};
207
208enum stm32mp1_pllcfg {
209 PLLCFG_M,
210 PLLCFG_N,
211 PLLCFG_P,
212 PLLCFG_Q,
213 PLLCFG_R,
214 PLLCFG_O,
215 PLLCFG_NB
216};
217
218enum stm32mp1_pllcsg {
219 PLLCSG_MOD_PER,
220 PLLCSG_INC_STEP,
221 PLLCSG_SSCG_MODE,
222 PLLCSG_NB
223};
224
225enum stm32mp1_plltype {
226 PLL_800,
227 PLL_1600,
228 PLL_TYPE_NB
229};
230
231struct stm32mp1_pll {
232 uint8_t refclk_min;
233 uint8_t refclk_max;
234 uint8_t divn_max;
235};
236
237struct stm32mp1_clk_gate {
238 uint16_t offset;
239 uint8_t bit;
240 uint8_t index;
241 uint8_t set_clr;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100242 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */
243 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */
Yann Gautier9aea69e2018-07-24 17:13:36 +0200244};
245
246struct stm32mp1_clk_sel {
247 uint16_t offset;
248 uint8_t src;
249 uint8_t msk;
250 uint8_t nb_parent;
251 const uint8_t *parent;
252};
253
254#define REFCLK_SIZE 4
255struct stm32mp1_clk_pll {
256 enum stm32mp1_plltype plltype;
257 uint16_t rckxselr;
258 uint16_t pllxcfgr1;
259 uint16_t pllxcfgr2;
260 uint16_t pllxfracr;
261 uint16_t pllxcr;
262 uint16_t pllxcsgr;
263 enum stm32mp_osc_id refclk[REFCLK_SIZE];
264};
265
Yann Gautiere4a3c352019-02-14 10:53:33 +0100266/* Clocks with selectable source and non set/clr register access */
267#define _CLK_SELEC(off, b, idx, s) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200268 { \
269 .offset = (off), \
270 .bit = (b), \
271 .index = (idx), \
272 .set_clr = 0, \
273 .sel = (s), \
274 .fixed = _UNKNOWN_ID, \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200275 }
276
Yann Gautiere4a3c352019-02-14 10:53:33 +0100277/* Clocks with fixed source and non set/clr register access */
278#define _CLK_FIXED(off, b, idx, f) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200279 { \
280 .offset = (off), \
281 .bit = (b), \
282 .index = (idx), \
283 .set_clr = 0, \
284 .sel = _UNKNOWN_SEL, \
285 .fixed = (f), \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200286 }
287
Yann Gautiere4a3c352019-02-14 10:53:33 +0100288/* Clocks with selectable source and set/clr register access */
289#define _CLK_SC_SELEC(off, b, idx, s) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200290 { \
291 .offset = (off), \
292 .bit = (b), \
293 .index = (idx), \
294 .set_clr = 1, \
295 .sel = (s), \
296 .fixed = _UNKNOWN_ID, \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200297 }
298
Yann Gautiere4a3c352019-02-14 10:53:33 +0100299/* Clocks with fixed source and set/clr register access */
300#define _CLK_SC_FIXED(off, b, idx, f) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200301 { \
302 .offset = (off), \
303 .bit = (b), \
304 .index = (idx), \
305 .set_clr = 1, \
306 .sel = _UNKNOWN_SEL, \
307 .fixed = (f), \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200308 }
309
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200310#define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \
311 [_ ## _label ## _SEL] = { \
312 .offset = _rcc_selr, \
313 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \
Etienne Carrierec164ce22019-12-08 08:20:40 +0100314 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \
315 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200316 .parent = (_parents), \
317 .nb_parent = ARRAY_SIZE(_parents) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200318 }
319
Yann Gautiere4a3c352019-02-14 10:53:33 +0100320#define _CLK_PLL(idx, type, off1, off2, off3, \
321 off4, off5, off6, \
322 p1, p2, p3, p4) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200323 [(idx)] = { \
324 .plltype = (type), \
325 .rckxselr = (off1), \
326 .pllxcfgr1 = (off2), \
327 .pllxcfgr2 = (off3), \
328 .pllxfracr = (off4), \
329 .pllxcr = (off5), \
330 .pllxcsgr = (off6), \
331 .refclk[0] = (p1), \
332 .refclk[1] = (p2), \
333 .refclk[2] = (p3), \
334 .refclk[3] = (p4), \
335 }
336
Yann Gautiere4a3c352019-02-14 10:53:33 +0100337#define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate)
338
Yann Gautier9aea69e2018-07-24 17:13:36 +0200339static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100340 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK),
341 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK),
342 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK),
343 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK),
344 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
345 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R),
346 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4),
347 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4),
348 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK),
349 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4),
350 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4),
351
352 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1),
353 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
354 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
355 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
356 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
357 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
358 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
359 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
360 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
361 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
362 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
363
364 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2),
365 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
366
Yann Gautier3edc7c32019-05-20 19:17:08 +0200367 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID),
368
Yann Gautiere4a3c352019-02-14 10:53:33 +0100369 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
370 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
371 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
372
373 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
374 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
375 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200376 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100377 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
378 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5),
379 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5),
380 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5),
381 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5),
382 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5),
383 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
384
385 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
386 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
387
388 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
389 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
390 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
391 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
392 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
393 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
394 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
395 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
396 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
397 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
398 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
399
400 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5),
401 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5),
402 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5),
403 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL),
404 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5),
405
406 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
407 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
408 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
409 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
410 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
411
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100412 _CLK_SELEC(RCC_BDCR, 20, RTC, _RTC_SEL),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100413 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
414};
415
416static const uint8_t i2c12_parents[] = {
417 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
418};
419
420static const uint8_t i2c35_parents[] = {
421 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
422};
423
424static const uint8_t stgen_parents[] = {
425 _HSI_KER, _HSE_KER
426};
427
428static const uint8_t i2c46_parents[] = {
429 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER
430};
431
432static const uint8_t spi6_parents[] = {
433 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q
434};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200435
Yann Gautiere4a3c352019-02-14 10:53:33 +0100436static const uint8_t usart1_parents[] = {
437 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER
438};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200439
Yann Gautiere4a3c352019-02-14 10:53:33 +0100440static const uint8_t rng1_parents[] = {
441 _CSI, _PLL4_R, _LSE, _LSI
442};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200443
Yann Gautiere4a3c352019-02-14 10:53:33 +0100444static const uint8_t uart6_parents[] = {
445 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
446};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200447
Yann Gautiere4a3c352019-02-14 10:53:33 +0100448static const uint8_t uart234578_parents[] = {
449 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
450};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200451
Yann Gautiere4a3c352019-02-14 10:53:33 +0100452static const uint8_t sdmmc12_parents[] = {
453 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER
454};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200455
Yann Gautiere4a3c352019-02-14 10:53:33 +0100456static const uint8_t sdmmc3_parents[] = {
457 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER
458};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200459
Yann Gautiere4a3c352019-02-14 10:53:33 +0100460static const uint8_t qspi_parents[] = {
461 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
462};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200463
Yann Gautiere4a3c352019-02-14 10:53:33 +0100464static const uint8_t fmc_parents[] = {
465 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
466};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200467
Yann Gautiere4a3c352019-02-14 10:53:33 +0100468static const uint8_t ass_parents[] = {
469 _HSI, _HSE, _PLL2
Yann Gautier9aea69e2018-07-24 17:13:36 +0200470};
471
Yann Gautiered342322019-02-15 17:33:27 +0100472static const uint8_t mss_parents[] = {
473 _HSI, _HSE, _CSI, _PLL3
474};
475
Yann Gautiere4a3c352019-02-14 10:53:33 +0100476static const uint8_t usbphy_parents[] = {
477 _HSE_KER, _PLL4_R, _HSE_KER_DIV2
478};
479
480static const uint8_t usbo_parents[] = {
481 _PLL4_R, _USB_PHY_48
482};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200483
Etienne Carriere04132612019-12-08 08:20:12 +0100484static const uint8_t mpu_parents[] = {
485 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */
486};
487
488static const uint8_t per_parents[] = {
489 _HSI, _HSE, _CSI,
490};
491
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100492static const uint8_t rtc_parents[] = {
493 _UNKNOWN_ID, _LSE, _LSI, _HSE
494};
495
Yann Gautier9aea69e2018-07-24 17:13:36 +0200496static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200497 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents),
498 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents),
499 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents),
500 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents),
501 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents),
502 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents),
503 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents),
Etienne Carriere04132612019-12-08 08:20:12 +0100504 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents),
505 _CLK_PARENT_SEL(PER, RCC_CPERCKSELR, per_parents),
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100506 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents),
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200507 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents),
508 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents),
509 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents),
510 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents),
511 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents),
512 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents),
513 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents),
514 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents),
515 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents),
516 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents),
517 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents),
518 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents),
Yann Gautier9aea69e2018-07-24 17:13:36 +0200519};
520
521/* Define characteristic of PLL according type */
522#define DIVN_MIN 24
523static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
524 [PLL_800] = {
525 .refclk_min = 4,
526 .refclk_max = 16,
527 .divn_max = 99,
528 },
529 [PLL_1600] = {
530 .refclk_min = 8,
531 .refclk_max = 16,
532 .divn_max = 199,
533 },
534};
535
536/* PLLNCFGR2 register divider by output */
537static const uint8_t pllncfgr2[_DIV_NB] = {
538 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
539 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
Yann Gautiere4a3c352019-02-14 10:53:33 +0100540 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200541};
542
543static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100544 _CLK_PLL(_PLL1, PLL_1600,
545 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
546 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
547 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
548 _CLK_PLL(_PLL2, PLL_1600,
549 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
550 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
551 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
552 _CLK_PLL(_PLL3, PLL_800,
553 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
554 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
555 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID),
556 _CLK_PLL(_PLL4, PLL_800,
557 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
558 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
559 _HSI, _HSE, _CSI, _I2S_CKIN),
Yann Gautier9aea69e2018-07-24 17:13:36 +0200560};
561
562/* Prescaler table lookups for clock computation */
Yann Gautiered342322019-02-15 17:33:27 +0100563/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
564static const uint8_t stm32mp1_mcu_div[16] = {
565 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
566};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200567
568/* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */
569#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
570#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
571static const uint8_t stm32mp1_mpu_apbx_div[8] = {
572 0, 1, 2, 3, 4, 4, 4, 4
573};
574
575/* div = /1 /2 /3 /4 */
576static const uint8_t stm32mp1_axi_div[8] = {
577 1, 2, 3, 4, 4, 4, 4, 4
578};
579
Yann Gautiere4a3c352019-02-14 10:53:33 +0100580/* RCC clock device driver private */
581static unsigned long stm32mp1_osc[NB_OSC];
582static struct spinlock reg_lock;
583static unsigned int gate_refcounts[NB_GATES];
584static struct spinlock refcount_lock;
585
586static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx)
587{
588 return &stm32mp1_clk_gate[idx];
589}
Yann Gautier9aea69e2018-07-24 17:13:36 +0200590
Yann Gautiere4a3c352019-02-14 10:53:33 +0100591static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx)
592{
593 return &stm32mp1_clk_sel[idx];
594}
Yann Gautier9aea69e2018-07-24 17:13:36 +0200595
Yann Gautiere4a3c352019-02-14 10:53:33 +0100596static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx)
597{
598 return &stm32mp1_clk_pll[idx];
599}
600
Yann Gautiere4a3c352019-02-14 10:53:33 +0100601static void stm32mp1_clk_lock(struct spinlock *lock)
602{
Yann Gautierf540a592019-05-22 19:13:51 +0200603 if (stm32mp_lock_available()) {
604 /* Assume interrupts are masked */
605 spin_lock(lock);
Yann Gautiere4a3c352019-02-14 10:53:33 +0100606 }
Yann Gautiere4a3c352019-02-14 10:53:33 +0100607}
608
609static void stm32mp1_clk_unlock(struct spinlock *lock)
610{
Yann Gautierf540a592019-05-22 19:13:51 +0200611 if (stm32mp_lock_available()) {
612 spin_unlock(lock);
Yann Gautiere4a3c352019-02-14 10:53:33 +0100613 }
Yann Gautiere4a3c352019-02-14 10:53:33 +0100614}
615
616bool stm32mp1_rcc_is_secure(void)
617{
618 uintptr_t rcc_base = stm32mp_rcc_base();
619
620 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0;
621}
622
Yann Gautiered342322019-02-15 17:33:27 +0100623bool stm32mp1_rcc_is_mckprot(void)
624{
625 uintptr_t rcc_base = stm32mp_rcc_base();
626
627 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_MCKPROT) != 0;
628}
629
Yann Gautiere4a3c352019-02-14 10:53:33 +0100630void stm32mp1_clk_rcc_regs_lock(void)
631{
632 stm32mp1_clk_lock(&reg_lock);
633}
634
635void stm32mp1_clk_rcc_regs_unlock(void)
636{
637 stm32mp1_clk_unlock(&reg_lock);
638}
639
640static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200641{
642 if (idx >= NB_OSC) {
643 return 0;
644 }
645
Yann Gautiere4a3c352019-02-14 10:53:33 +0100646 return stm32mp1_osc[idx];
Yann Gautier9aea69e2018-07-24 17:13:36 +0200647}
648
Yann Gautiere4a3c352019-02-14 10:53:33 +0100649static int stm32mp1_clk_get_gated_id(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200650{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100651 unsigned int i;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200652
Yann Gautiere4a3c352019-02-14 10:53:33 +0100653 for (i = 0U; i < NB_GATES; i++) {
654 if (gate_ref(i)->index == id) {
Yann Gautier9aea69e2018-07-24 17:13:36 +0200655 return i;
656 }
657 }
658
659 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id);
660
661 return -EINVAL;
662}
663
Yann Gautiere4a3c352019-02-14 10:53:33 +0100664static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200665{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100666 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200667}
668
Yann Gautiere4a3c352019-02-14 10:53:33 +0100669static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200670{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100671 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200672}
673
Yann Gautiere4a3c352019-02-14 10:53:33 +0100674static int stm32mp1_clk_get_parent(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200675{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100676 const struct stm32mp1_clk_sel *sel;
Etienne Carriere04132612019-12-08 08:20:12 +0100677 uint32_t p_sel;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200678 int i;
679 enum stm32mp1_parent_id p;
680 enum stm32mp1_parent_sel s;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100681 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200682
Etienne Carriere04132612019-12-08 08:20:12 +0100683 /* Few non gateable clock have a static parent ID, find them */
684 i = (int)clock_id2parent_id(id);
685 if (i != _UNKNOWN_ID) {
686 return i;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200687 }
688
Yann Gautiere4a3c352019-02-14 10:53:33 +0100689 i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200690 if (i < 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100691 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200692 }
693
Yann Gautiere4a3c352019-02-14 10:53:33 +0100694 p = stm32mp1_clk_get_fixed_parent(i);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200695 if (p < _PARENT_NB) {
696 return (int)p;
697 }
698
Yann Gautiere4a3c352019-02-14 10:53:33 +0100699 s = stm32mp1_clk_get_sel(i);
700 if (s == _UNKNOWN_SEL) {
Yann Gautier9aea69e2018-07-24 17:13:36 +0200701 return -EINVAL;
702 }
Yann Gautiere4a3c352019-02-14 10:53:33 +0100703 if (s >= _PARENT_SEL_NB) {
704 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200705 }
706
Yann Gautiere4a3c352019-02-14 10:53:33 +0100707 sel = clk_sel_ref(s);
Etienne Carrierec164ce22019-12-08 08:20:40 +0100708 p_sel = (mmio_read_32(rcc_base + sel->offset) &
709 (sel->msk << sel->src)) >> sel->src;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100710 if (p_sel < sel->nb_parent) {
711 return (int)sel->parent[p_sel];
712 }
Yann Gautier9aea69e2018-07-24 17:13:36 +0200713
714 return -EINVAL;
715}
716
Yann Gautiere4a3c352019-02-14 10:53:33 +0100717static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200718{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100719 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr);
720 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200721
Yann Gautiere4a3c352019-02-14 10:53:33 +0100722 return stm32mp1_clk_get_fixed(pll->refclk[src]);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200723}
724
725/*
726 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
727 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
728 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
729 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
730 */
Yann Gautiere4a3c352019-02-14 10:53:33 +0100731static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200732{
Yann Gautier9aea69e2018-07-24 17:13:36 +0200733 unsigned long refclk, fvco;
734 uint32_t cfgr1, fracr, divm, divn;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100735 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200736
Yann Gautiere4a3c352019-02-14 10:53:33 +0100737 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1);
738 fracr = mmio_read_32(rcc_base + pll->pllxfracr);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200739
740 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
741 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
742
Yann Gautiere4a3c352019-02-14 10:53:33 +0100743 refclk = stm32mp1_pll_get_fref(pll);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200744
745 /*
746 * With FRACV :
747 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
748 * Without FRACV
749 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
750 */
751 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100752 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >>
753 RCC_PLLNFRACR_FRACV_SHIFT;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200754 unsigned long long numerator, denominator;
755
Yann Gautiere4a3c352019-02-14 10:53:33 +0100756 numerator = (((unsigned long long)divn + 1U) << 13) + fracv;
757 numerator = refclk * numerator;
758 denominator = ((unsigned long long)divm + 1U) << 13;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200759 fvco = (unsigned long)(numerator / denominator);
760 } else {
761 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U));
762 }
763
764 return fvco;
765}
766
Yann Gautiere4a3c352019-02-14 10:53:33 +0100767static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200768 enum stm32mp1_div_id div_id)
769{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100770 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200771 unsigned long dfout;
772 uint32_t cfgr2, divy;
773
774 if (div_id >= _DIV_NB) {
775 return 0;
776 }
777
Yann Gautiere4a3c352019-02-14 10:53:33 +0100778 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200779 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
780
Yann Gautiere4a3c352019-02-14 10:53:33 +0100781 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200782
783 return dfout;
784}
785
Yann Gautiere4a3c352019-02-14 10:53:33 +0100786static unsigned long get_clock_rate(int p)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200787{
788 uint32_t reg, clkdiv;
789 unsigned long clock = 0;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100790 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200791
792 switch (p) {
793 case _CK_MPU:
794 /* MPU sub system */
Yann Gautiere4a3c352019-02-14 10:53:33 +0100795 reg = mmio_read_32(rcc_base + RCC_MPCKSELR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200796 switch (reg & RCC_SELR_SRC_MASK) {
797 case RCC_MPCKSELR_HSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100798 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200799 break;
800 case RCC_MPCKSELR_HSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100801 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200802 break;
803 case RCC_MPCKSELR_PLL:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100804 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200805 break;
806 case RCC_MPCKSELR_PLL_MPUDIV:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100807 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200808
Yann Gautiere4a3c352019-02-14 10:53:33 +0100809 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200810 clkdiv = reg & RCC_MPUDIV_MASK;
811 if (clkdiv != 0U) {
812 clock /= stm32mp1_mpu_div[clkdiv];
813 }
Yann Gautier9aea69e2018-07-24 17:13:36 +0200814 break;
815 default:
816 break;
817 }
818 break;
819 /* AXI sub system */
820 case _ACLK:
821 case _HCLK2:
822 case _HCLK6:
823 case _PCLK4:
824 case _PCLK5:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100825 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200826 switch (reg & RCC_SELR_SRC_MASK) {
827 case RCC_ASSCKSELR_HSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100828 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200829 break;
830 case RCC_ASSCKSELR_HSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100831 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200832 break;
833 case RCC_ASSCKSELR_PLL:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100834 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200835 break;
836 default:
837 break;
838 }
839
840 /* System clock divider */
Yann Gautiere4a3c352019-02-14 10:53:33 +0100841 reg = mmio_read_32(rcc_base + RCC_AXIDIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200842 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
843
844 switch (p) {
845 case _PCLK4:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100846 reg = mmio_read_32(rcc_base + RCC_APB4DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200847 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
848 break;
849 case _PCLK5:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100850 reg = mmio_read_32(rcc_base + RCC_APB5DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200851 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
852 break;
853 default:
854 break;
855 }
856 break;
Yann Gautiered342322019-02-15 17:33:27 +0100857 /* MCU sub system */
858 case _CK_MCU:
859 case _PCLK1:
860 case _PCLK2:
861 case _PCLK3:
862 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR);
863 switch (reg & RCC_SELR_SRC_MASK) {
864 case RCC_MSSCKSELR_HSI:
865 clock = stm32mp1_clk_get_fixed(_HSI);
866 break;
867 case RCC_MSSCKSELR_HSE:
868 clock = stm32mp1_clk_get_fixed(_HSE);
869 break;
870 case RCC_MSSCKSELR_CSI:
871 clock = stm32mp1_clk_get_fixed(_CSI);
872 break;
873 case RCC_MSSCKSELR_PLL:
874 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
875 break;
876 default:
877 break;
878 }
879
880 /* MCU clock divider */
881 reg = mmio_read_32(rcc_base + RCC_MCUDIVR);
882 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
883
884 switch (p) {
885 case _PCLK1:
886 reg = mmio_read_32(rcc_base + RCC_APB1DIVR);
887 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
888 break;
889 case _PCLK2:
890 reg = mmio_read_32(rcc_base + RCC_APB2DIVR);
891 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
892 break;
893 case _PCLK3:
894 reg = mmio_read_32(rcc_base + RCC_APB3DIVR);
895 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
896 break;
897 case _CK_MCU:
898 default:
899 break;
900 }
901 break;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200902 case _CK_PER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100903 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200904 switch (reg & RCC_SELR_SRC_MASK) {
905 case RCC_CPERCKSELR_HSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100906 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200907 break;
908 case RCC_CPERCKSELR_HSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100909 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200910 break;
911 case RCC_CPERCKSELR_CSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100912 clock = stm32mp1_clk_get_fixed(_CSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200913 break;
914 default:
915 break;
916 }
917 break;
918 case _HSI:
919 case _HSI_KER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100920 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200921 break;
922 case _CSI:
923 case _CSI_KER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100924 clock = stm32mp1_clk_get_fixed(_CSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200925 break;
926 case _HSE:
927 case _HSE_KER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100928 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200929 break;
930 case _HSE_KER_DIV2:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100931 clock = stm32mp1_clk_get_fixed(_HSE) >> 1;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200932 break;
933 case _LSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100934 clock = stm32mp1_clk_get_fixed(_LSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200935 break;
936 case _LSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100937 clock = stm32mp1_clk_get_fixed(_LSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200938 break;
939 /* PLL */
940 case _PLL1_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100941 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200942 break;
943 case _PLL1_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100944 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200945 break;
946 case _PLL1_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100947 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200948 break;
949 case _PLL2_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100950 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200951 break;
952 case _PLL2_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100953 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200954 break;
955 case _PLL2_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100956 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200957 break;
958 case _PLL3_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100959 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200960 break;
961 case _PLL3_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100962 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200963 break;
964 case _PLL3_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100965 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200966 break;
967 case _PLL4_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100968 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200969 break;
970 case _PLL4_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100971 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200972 break;
973 case _PLL4_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100974 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200975 break;
976 /* Other */
977 case _USB_PHY_48:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100978 clock = USB_PHY_48_MHZ;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200979 break;
980 default:
981 break;
982 }
983
984 return clock;
985}
986
Yann Gautiere4a3c352019-02-14 10:53:33 +0100987static void __clk_enable(struct stm32mp1_clk_gate const *gate)
988{
989 uintptr_t rcc_base = stm32mp_rcc_base();
990
Etienne Carriere8a668892019-12-08 08:21:08 +0100991 VERBOSE("Enable clock %u\n", gate->index);
992
Yann Gautiere4a3c352019-02-14 10:53:33 +0100993 if (gate->set_clr != 0U) {
994 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit));
995 } else {
996 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit));
997 }
Yann Gautiere4a3c352019-02-14 10:53:33 +0100998}
999
1000static void __clk_disable(struct stm32mp1_clk_gate const *gate)
1001{
1002 uintptr_t rcc_base = stm32mp_rcc_base();
1003
Etienne Carriere8a668892019-12-08 08:21:08 +01001004 VERBOSE("Disable clock %u\n", gate->index);
1005
Yann Gautiere4a3c352019-02-14 10:53:33 +01001006 if (gate->set_clr != 0U) {
1007 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET,
1008 BIT(gate->bit));
1009 } else {
1010 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit));
1011 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001012}
1013
1014static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate)
1015{
1016 uintptr_t rcc_base = stm32mp_rcc_base();
1017
1018 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit);
1019}
1020
1021unsigned int stm32mp1_clk_get_refcount(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001022{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001023 int i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001024
1025 if (i < 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001026 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001027 }
1028
Yann Gautiere4a3c352019-02-14 10:53:33 +01001029 return gate_refcounts[i];
Yann Gautier9aea69e2018-07-24 17:13:36 +02001030}
1031
Etienne Carriere481aa002019-12-08 08:21:44 +01001032/* Oscillators and PLLs are not gated at runtime */
1033static bool clock_is_always_on(unsigned long id)
1034{
1035 switch (id) {
1036 case CK_HSE:
1037 case CK_CSI:
1038 case CK_LSI:
1039 case CK_LSE:
1040 case CK_HSI:
1041 case CK_HSE_DIV2:
1042 case PLL1_Q:
1043 case PLL1_R:
1044 case PLL2_P:
1045 case PLL2_Q:
1046 case PLL2_R:
1047 case PLL3_P:
1048 case PLL3_Q:
1049 case PLL3_R:
1050 return true;
1051 default:
1052 return false;
1053 }
1054}
1055
Yann Gautiere4a3c352019-02-14 10:53:33 +01001056void __stm32mp1_clk_enable(unsigned long id, bool secure)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001057{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001058 const struct stm32mp1_clk_gate *gate;
Etienne Carriere481aa002019-12-08 08:21:44 +01001059 int i;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001060 unsigned int *refcnt;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001061
Etienne Carriere481aa002019-12-08 08:21:44 +01001062 if (clock_is_always_on(id)) {
1063 return;
1064 }
1065
1066 i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001067 if (i < 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001068 ERROR("Clock %d can't be enabled\n", (uint32_t)id);
1069 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001070 }
1071
Yann Gautiere4a3c352019-02-14 10:53:33 +01001072 gate = gate_ref(i);
1073 refcnt = &gate_refcounts[i];
1074
1075 stm32mp1_clk_lock(&refcount_lock);
1076
1077 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) {
1078 __clk_enable(gate);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001079 }
1080
Yann Gautiere4a3c352019-02-14 10:53:33 +01001081 stm32mp1_clk_unlock(&refcount_lock);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001082}
1083
Yann Gautiere4a3c352019-02-14 10:53:33 +01001084void __stm32mp1_clk_disable(unsigned long id, bool secure)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001085{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001086 const struct stm32mp1_clk_gate *gate;
Etienne Carriere481aa002019-12-08 08:21:44 +01001087 int i;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001088 unsigned int *refcnt;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001089
Etienne Carriere481aa002019-12-08 08:21:44 +01001090 if (clock_is_always_on(id)) {
1091 return;
1092 }
1093
1094 i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001095 if (i < 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001096 ERROR("Clock %d can't be disabled\n", (uint32_t)id);
1097 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001098 }
1099
Yann Gautiere4a3c352019-02-14 10:53:33 +01001100 gate = gate_ref(i);
1101 refcnt = &gate_refcounts[i];
1102
1103 stm32mp1_clk_lock(&refcount_lock);
1104
1105 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) {
1106 __clk_disable(gate);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001107 }
1108
Yann Gautiere4a3c352019-02-14 10:53:33 +01001109 stm32mp1_clk_unlock(&refcount_lock);
1110}
1111
1112void stm32mp_clk_enable(unsigned long id)
1113{
1114 __stm32mp1_clk_enable(id, true);
1115}
1116
1117void stm32mp_clk_disable(unsigned long id)
1118{
1119 __stm32mp1_clk_disable(id, true);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001120}
1121
Yann Gautiere4a3c352019-02-14 10:53:33 +01001122bool stm32mp_clk_is_enabled(unsigned long id)
1123{
Etienne Carriere481aa002019-12-08 08:21:44 +01001124 int i;
1125
1126 if (clock_is_always_on(id)) {
1127 return true;
1128 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001129
Etienne Carriere481aa002019-12-08 08:21:44 +01001130 i = stm32mp1_clk_get_gated_id(id);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001131 if (i < 0) {
1132 panic();
1133 }
1134
1135 return __clk_is_enabled(gate_ref(i));
1136}
1137
Yann Gautiera2e2a302019-02-14 11:13:39 +01001138unsigned long stm32mp_clk_get_rate(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001139{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001140 int p = stm32mp1_clk_get_parent(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001141
1142 if (p < 0) {
1143 return 0;
1144 }
1145
Yann Gautiere4a3c352019-02-14 10:53:33 +01001146 return get_clock_rate(p);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001147}
1148
Yann Gautiere4a3c352019-02-14 10:53:33 +01001149static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001150{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001151 uintptr_t address = stm32mp_rcc_base() + offset;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001152
Yann Gautiere4a3c352019-02-14 10:53:33 +01001153 if (enable) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001154 mmio_setbits_32(address, mask_on);
1155 } else {
1156 mmio_clrbits_32(address, mask_on);
1157 }
1158}
1159
Yann Gautiere4a3c352019-02-14 10:53:33 +01001160static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001161{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001162 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR;
1163 uintptr_t address = stm32mp_rcc_base() + offset;
1164
1165 mmio_write_32(address, mask_on);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001166}
1167
Yann Gautiere4a3c352019-02-14 10:53:33 +01001168static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001169{
Yann Gautier2299d572019-02-14 11:14:39 +01001170 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001171 uint32_t mask_test;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001172 uintptr_t address = stm32mp_rcc_base() + offset;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001173
Yann Gautiere4a3c352019-02-14 10:53:33 +01001174 if (enable) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001175 mask_test = mask_rdy;
1176 } else {
1177 mask_test = 0;
1178 }
1179
Yann Gautier2299d572019-02-14 11:14:39 +01001180 timeout = timeout_init_us(OSCRDY_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001181 while ((mmio_read_32(address) & mask_rdy) != mask_test) {
Yann Gautier2299d572019-02-14 11:14:39 +01001182 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001183 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001184 mask_rdy, address, enable, mmio_read_32(address));
1185 return -ETIMEDOUT;
1186 }
1187 }
1188
1189 return 0;
1190}
1191
Yann Gautiere4a3c352019-02-14 10:53:33 +01001192static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001193{
1194 uint32_t value;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001195 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001196
Yann Gautiere4a3c352019-02-14 10:53:33 +01001197 if (digbyp) {
1198 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001199 }
1200
Yann Gautiere4a3c352019-02-14 10:53:33 +01001201 if (bypass || digbyp) {
1202 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP);
1203 }
1204
Yann Gautier9aea69e2018-07-24 17:13:36 +02001205 /*
1206 * Warning: not recommended to switch directly from "high drive"
1207 * to "medium low drive", and vice-versa.
1208 */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001209 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>
Yann Gautier9aea69e2018-07-24 17:13:36 +02001210 RCC_BDCR_LSEDRV_SHIFT;
1211
1212 while (value != lsedrv) {
1213 if (value > lsedrv) {
1214 value--;
1215 } else {
1216 value++;
1217 }
1218
Yann Gautiere4a3c352019-02-14 10:53:33 +01001219 mmio_clrsetbits_32(rcc_base + RCC_BDCR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001220 RCC_BDCR_LSEDRV_MASK,
1221 value << RCC_BDCR_LSEDRV_SHIFT);
1222 }
1223
Yann Gautiere4a3c352019-02-14 10:53:33 +01001224 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001225}
1226
Yann Gautiere4a3c352019-02-14 10:53:33 +01001227static void stm32mp1_lse_wait(void)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001228{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001229 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001230 VERBOSE("%s: failed\n", __func__);
1231 }
1232}
1233
Yann Gautiere4a3c352019-02-14 10:53:33 +01001234static void stm32mp1_lsi_set(bool enable)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001235{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001236 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION);
1237
1238 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001239 VERBOSE("%s: failed\n", __func__);
1240 }
1241}
1242
Yann Gautiere4a3c352019-02-14 10:53:33 +01001243static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001244{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001245 uintptr_t rcc_base = stm32mp_rcc_base();
1246
1247 if (digbyp) {
1248 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001249 }
1250
Yann Gautiere4a3c352019-02-14 10:53:33 +01001251 if (bypass || digbyp) {
1252 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1253 }
1254
1255 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON);
1256 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001257 VERBOSE("%s: failed\n", __func__);
1258 }
1259
1260 if (css) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001261 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001262 }
1263}
1264
Yann Gautiere4a3c352019-02-14 10:53:33 +01001265static void stm32mp1_csi_set(bool enable)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001266{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001267 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION);
1268 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001269 VERBOSE("%s: failed\n", __func__);
1270 }
1271}
1272
Yann Gautiere4a3c352019-02-14 10:53:33 +01001273static void stm32mp1_hsi_set(bool enable)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001274{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001275 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION);
1276 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001277 VERBOSE("%s: failed\n", __func__);
1278 }
1279}
1280
Yann Gautiere4a3c352019-02-14 10:53:33 +01001281static int stm32mp1_set_hsidiv(uint8_t hsidiv)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001282{
Yann Gautier2299d572019-02-14 11:14:39 +01001283 uint64_t timeout;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001284 uintptr_t rcc_base = stm32mp_rcc_base();
1285 uintptr_t address = rcc_base + RCC_OCRDYR;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001286
Yann Gautiere4a3c352019-02-14 10:53:33 +01001287 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001288 RCC_HSICFGR_HSIDIV_MASK,
1289 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv);
1290
Yann Gautier2299d572019-02-14 11:14:39 +01001291 timeout = timeout_init_us(HSIDIV_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001292 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001293 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001294 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001295 address, mmio_read_32(address));
1296 return -ETIMEDOUT;
1297 }
1298 }
1299
1300 return 0;
1301}
1302
Yann Gautiere4a3c352019-02-14 10:53:33 +01001303static int stm32mp1_hsidiv(unsigned long hsifreq)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001304{
1305 uint8_t hsidiv;
1306 uint32_t hsidivfreq = MAX_HSI_HZ;
1307
1308 for (hsidiv = 0; hsidiv < 4U; hsidiv++) {
1309 if (hsidivfreq == hsifreq) {
1310 break;
1311 }
1312
1313 hsidivfreq /= 2U;
1314 }
1315
1316 if (hsidiv == 4U) {
1317 ERROR("Invalid clk-hsi frequency\n");
1318 return -1;
1319 }
1320
1321 if (hsidiv != 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001322 return stm32mp1_set_hsidiv(hsidiv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001323 }
1324
1325 return 0;
1326}
1327
Yann Gautiere4a3c352019-02-14 10:53:33 +01001328static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,
1329 unsigned int clksrc,
1330 uint32_t *pllcfg, int plloff)
1331{
1332 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1333 uintptr_t rcc_base = stm32mp_rcc_base();
1334 uintptr_t pllxcr = rcc_base + pll->pllxcr;
1335 enum stm32mp1_plltype type = pll->plltype;
1336 uintptr_t clksrc_address = rcc_base + (clksrc >> 4);
1337 unsigned long refclk;
1338 uint32_t ifrge = 0U;
Andre Przywara2d5690c2020-03-26 11:50:33 +00001339 uint32_t src, value, fracv = 0;
1340 void *fdt;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001341
1342 /* Check PLL output */
1343 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) {
1344 return false;
1345 }
1346
1347 /* Check current clksrc */
1348 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK;
1349 if (src != (clksrc & RCC_SELR_SRC_MASK)) {
1350 return false;
1351 }
1352
1353 /* Check Div */
1354 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK;
1355
1356 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
1357 (pllcfg[PLLCFG_M] + 1U);
1358
1359 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1360 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1361 return false;
1362 }
1363
1364 if ((type == PLL_800) && (refclk >= 8000000U)) {
1365 ifrge = 1U;
1366 }
1367
1368 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1369 RCC_PLLNCFGR1_DIVN_MASK;
1370 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1371 RCC_PLLNCFGR1_DIVM_MASK;
1372 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1373 RCC_PLLNCFGR1_IFRGE_MASK;
1374 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) {
1375 return false;
1376 }
1377
1378 /* Fractional configuration */
Andre Przywara2d5690c2020-03-26 11:50:33 +00001379 if (fdt_get_address(&fdt) == 1) {
1380 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0);
1381 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001382
1383 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
1384 value |= RCC_PLLNFRACR_FRACLE;
1385 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {
1386 return false;
1387 }
1388
1389 /* Output config */
1390 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1391 RCC_PLLNCFGR2_DIVP_MASK;
1392 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1393 RCC_PLLNCFGR2_DIVQ_MASK;
1394 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1395 RCC_PLLNCFGR2_DIVR_MASK;
1396 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) {
1397 return false;
1398 }
1399
1400 return true;
1401}
1402
1403static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001404{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001405 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1406 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001407
Yann Gautierd0dcbaa2019-06-04 15:55:37 +02001408 /* Preserve RCC_PLLNCR_SSCG_CTRL value */
1409 mmio_clrsetbits_32(pllxcr,
1410 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1411 RCC_PLLNCR_DIVREN,
1412 RCC_PLLNCR_PLLON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001413}
1414
Yann Gautiere4a3c352019-02-14 10:53:33 +01001415static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001416{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001417 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1418 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
Yann Gautier2299d572019-02-14 11:14:39 +01001419 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001420
Yann Gautier9aea69e2018-07-24 17:13:36 +02001421 /* Wait PLL lock */
1422 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001423 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001424 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001425 pll_id, pllxcr, mmio_read_32(pllxcr));
1426 return -ETIMEDOUT;
1427 }
1428 }
1429
1430 /* Start the requested output */
1431 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1432
1433 return 0;
1434}
1435
Yann Gautiere4a3c352019-02-14 10:53:33 +01001436static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001437{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001438 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1439 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
Yann Gautier2299d572019-02-14 11:14:39 +01001440 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001441
1442 /* Stop all output */
1443 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1444 RCC_PLLNCR_DIVREN);
1445
1446 /* Stop PLL */
1447 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON);
1448
Yann Gautier2299d572019-02-14 11:14:39 +01001449 timeout = timeout_init_us(PLLRDY_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001450 /* Wait PLL stopped */
1451 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001452 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001453 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001454 pll_id, pllxcr, mmio_read_32(pllxcr));
1455 return -ETIMEDOUT;
1456 }
1457 }
1458
1459 return 0;
1460}
1461
Yann Gautiere4a3c352019-02-14 10:53:33 +01001462static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001463 uint32_t *pllcfg)
1464{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001465 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1466 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001467 uint32_t value;
1468
1469 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1470 RCC_PLLNCFGR2_DIVP_MASK;
1471 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1472 RCC_PLLNCFGR2_DIVQ_MASK;
1473 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1474 RCC_PLLNCFGR2_DIVR_MASK;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001475 mmio_write_32(rcc_base + pll->pllxcfgr2, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001476}
1477
Yann Gautiere4a3c352019-02-14 10:53:33 +01001478static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001479 uint32_t *pllcfg, uint32_t fracv)
1480{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001481 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1482 uintptr_t rcc_base = stm32mp_rcc_base();
1483 enum stm32mp1_plltype type = pll->plltype;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001484 unsigned long refclk;
1485 uint32_t ifrge = 0;
1486 uint32_t src, value;
1487
Yann Gautiere4a3c352019-02-14 10:53:33 +01001488 src = mmio_read_32(rcc_base + pll->rckxselr) &
Yann Gautier9aea69e2018-07-24 17:13:36 +02001489 RCC_SELR_REFCLK_SRC_MASK;
1490
Yann Gautiere4a3c352019-02-14 10:53:33 +01001491 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
Yann Gautier9aea69e2018-07-24 17:13:36 +02001492 (pllcfg[PLLCFG_M] + 1U);
1493
1494 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1495 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1496 return -EINVAL;
1497 }
1498
1499 if ((type == PLL_800) && (refclk >= 8000000U)) {
1500 ifrge = 1U;
1501 }
1502
1503 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1504 RCC_PLLNCFGR1_DIVN_MASK;
1505 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1506 RCC_PLLNCFGR1_DIVM_MASK;
1507 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1508 RCC_PLLNCFGR1_IFRGE_MASK;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001509 mmio_write_32(rcc_base + pll->pllxcfgr1, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001510
1511 /* Fractional configuration */
1512 value = 0;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001513 mmio_write_32(rcc_base + pll->pllxfracr, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001514
1515 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001516 mmio_write_32(rcc_base + pll->pllxfracr, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001517
1518 value |= RCC_PLLNFRACR_FRACLE;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001519 mmio_write_32(rcc_base + pll->pllxfracr, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001520
Yann Gautiere4a3c352019-02-14 10:53:33 +01001521 stm32mp1_pll_config_output(pll_id, pllcfg);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001522
1523 return 0;
1524}
1525
Yann Gautiere4a3c352019-02-14 10:53:33 +01001526static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001527{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001528 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001529 uint32_t pllxcsg = 0;
1530
1531 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1532 RCC_PLLNCSGR_MOD_PER_MASK;
1533
1534 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1535 RCC_PLLNCSGR_INC_STEP_MASK;
1536
1537 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1538 RCC_PLLNCSGR_SSCG_MODE_MASK;
1539
Yann Gautiere4a3c352019-02-14 10:53:33 +01001540 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg);
Yann Gautierd0dcbaa2019-06-04 15:55:37 +02001541
1542 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr,
1543 RCC_PLLNCR_SSCG_CTRL);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001544}
1545
Yann Gautiere4a3c352019-02-14 10:53:33 +01001546static int stm32mp1_set_clksrc(unsigned int clksrc)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001547{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001548 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
Yann Gautier2299d572019-02-14 11:14:39 +01001549 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001550
Yann Gautiere4a3c352019-02-14 10:53:33 +01001551 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001552 clksrc & RCC_SELR_SRC_MASK);
1553
Yann Gautier2299d572019-02-14 11:14:39 +01001554 timeout = timeout_init_us(CLKSRC_TIMEOUT);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001555 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001556 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001557 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc,
1558 clksrc_address, mmio_read_32(clksrc_address));
Yann Gautier9aea69e2018-07-24 17:13:36 +02001559 return -ETIMEDOUT;
1560 }
1561 }
1562
1563 return 0;
1564}
1565
Yann Gautiere4a3c352019-02-14 10:53:33 +01001566static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001567{
Yann Gautier2299d572019-02-14 11:14:39 +01001568 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001569
1570 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK,
1571 clkdiv & RCC_DIVR_DIV_MASK);
1572
Yann Gautier2299d572019-02-14 11:14:39 +01001573 timeout = timeout_init_us(CLKDIV_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001574 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001575 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001576 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001577 clkdiv, address, mmio_read_32(address));
1578 return -ETIMEDOUT;
1579 }
1580 }
1581
1582 return 0;
1583}
1584
Yann Gautiere4a3c352019-02-14 10:53:33 +01001585static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001586{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001587 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001588
1589 /*
1590 * Binding clksrc :
1591 * bit15-4 offset
1592 * bit3: disable
1593 * bit2-0: MCOSEL[2:0]
1594 */
1595 if ((clksrc & 0x8U) != 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001596 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001597 } else {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001598 mmio_clrsetbits_32(clksrc_address,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001599 RCC_MCOCFG_MCOSRC_MASK,
1600 clksrc & RCC_MCOCFG_MCOSRC_MASK);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001601 mmio_clrsetbits_32(clksrc_address,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001602 RCC_MCOCFG_MCODIV_MASK,
1603 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001604 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001605 }
1606}
1607
Yann Gautiere4a3c352019-02-14 10:53:33 +01001608static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001609{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001610 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001611
1612 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) ||
1613 (clksrc != (uint32_t)CLK_RTC_DISABLED)) {
1614 mmio_clrsetbits_32(address,
1615 RCC_BDCR_RTCSRC_MASK,
1616 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1617
1618 mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
1619 }
1620
1621 if (lse_css) {
1622 mmio_setbits_32(address, RCC_BDCR_LSECSSON);
1623 }
1624}
1625
Yann Gautiere4a3c352019-02-14 10:53:33 +01001626static void stm32mp1_stgen_config(void)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001627{
1628 uintptr_t stgen;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001629 uint32_t cntfid0;
1630 unsigned long rate;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001631 unsigned long long counter;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001632
1633 stgen = fdt_get_stgen_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001634 cntfid0 = mmio_read_32(stgen + CNTFID_OFF);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001635 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K));
Yann Gautier9aea69e2018-07-24 17:13:36 +02001636
Yann Gautiere4a3c352019-02-14 10:53:33 +01001637 if (cntfid0 == rate) {
1638 return;
1639 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001640
Yann Gautiere4a3c352019-02-14 10:53:33 +01001641 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1642 counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF);
1643 counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32;
1644 counter = (counter * rate / cntfid0);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001645
Yann Gautiere4a3c352019-02-14 10:53:33 +01001646 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter);
1647 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32));
1648 mmio_write_32(stgen + CNTFID_OFF, rate);
1649 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001650
Yann Gautiere4a3c352019-02-14 10:53:33 +01001651 write_cntfrq((u_register_t)rate);
1652
1653 /* Need to update timer with new frequency */
1654 generic_delay_timer_init();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001655}
1656
1657void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
1658{
1659 uintptr_t stgen;
1660 unsigned long long cnt;
1661
1662 stgen = fdt_get_stgen_base();
1663
1664 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) |
1665 mmio_read_32(stgen + CNTCVL_OFF);
1666
1667 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U;
1668
1669 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1670 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt);
1671 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32));
1672 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1673}
1674
Yann Gautiere4a3c352019-02-14 10:53:33 +01001675static void stm32mp1_pkcs_config(uint32_t pkcs)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001676{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001677 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001678 uint32_t value = pkcs & 0xFU;
1679 uint32_t mask = 0xFU;
1680
1681 if ((pkcs & BIT(31)) != 0U) {
1682 mask <<= 4;
1683 value <<= 4;
1684 }
1685
1686 mmio_clrsetbits_32(address, mask, value);
1687}
1688
1689int stm32mp1_clk_init(void)
1690{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001691 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001692 unsigned int clksrc[CLKSRC_NB];
1693 unsigned int clkdiv[CLKDIV_NB];
1694 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1695 int plloff[_PLL_NB];
1696 int ret, len;
1697 enum stm32mp1_pll_id i;
1698 bool lse_css = false;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001699 bool pll3_preserve = false;
1700 bool pll4_preserve = false;
1701 bool pll4_bootrom = false;
Yann Gautierf9af3bc2018-11-09 15:57:18 +01001702 const fdt32_t *pkcs_cell;
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001703 void *fdt;
1704
1705 if (fdt_get_address(&fdt) == 0) {
1706 return false;
1707 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001708
1709 /* Check status field to disable security */
1710 if (!fdt_get_rcc_secure_status()) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001711 mmio_write_32(rcc_base + RCC_TZCR, 0);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001712 }
1713
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001714 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB,
1715 clksrc);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001716 if (ret < 0) {
1717 return -FDT_ERR_NOTFOUND;
1718 }
1719
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001720 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB,
1721 clkdiv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001722 if (ret < 0) {
1723 return -FDT_ERR_NOTFOUND;
1724 }
1725
1726 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1727 char name[12];
1728
Antonio Nino Diaz00086e32018-08-16 16:46:06 +01001729 snprintf(name, sizeof(name), "st,pll@%d", i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001730 plloff[i] = fdt_rcc_subnode_offset(name);
1731
1732 if (!fdt_check_node(plloff[i])) {
1733 continue;
1734 }
1735
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001736 ret = fdt_read_uint32_array(fdt, plloff[i], "cfg",
1737 (int)PLLCFG_NB, pllcfg[i]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001738 if (ret < 0) {
1739 return -FDT_ERR_NOTFOUND;
1740 }
1741 }
1742
Yann Gautiere4a3c352019-02-14 10:53:33 +01001743 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1744 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001745
1746 /*
1747 * Switch ON oscillator found in device-tree.
1748 * Note: HSI already ON after BootROM stage.
1749 */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001750 if (stm32mp1_osc[_LSI] != 0U) {
1751 stm32mp1_lsi_set(true);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001752 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001753 if (stm32mp1_osc[_LSE] != 0U) {
1754 bool bypass, digbyp;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001755 uint32_t lsedrv;
1756
1757 bypass = fdt_osc_read_bool(_LSE, "st,bypass");
Yann Gautiere4a3c352019-02-14 10:53:33 +01001758 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass");
Yann Gautier9aea69e2018-07-24 17:13:36 +02001759 lse_css = fdt_osc_read_bool(_LSE, "st,css");
1760 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive",
1761 LSEDRV_MEDIUM_HIGH);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001762 stm32mp1_lse_enable(bypass, digbyp, lsedrv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001763 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001764 if (stm32mp1_osc[_HSE] != 0U) {
1765 bool bypass, digbyp, css;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001766
Yann Gautiere4a3c352019-02-14 10:53:33 +01001767 bypass = fdt_osc_read_bool(_HSE, "st,bypass");
1768 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass");
1769 css = fdt_osc_read_bool(_HSE, "st,css");
1770 stm32mp1_hse_enable(bypass, digbyp, css);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001771 }
1772 /*
1773 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1774 * => switch on CSI even if node is not present in device tree
1775 */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001776 stm32mp1_csi_set(true);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001777
1778 /* Come back to HSI */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001779 ret = stm32mp1_set_clksrc(CLK_MPU_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001780 if (ret != 0) {
1781 return ret;
1782 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001783 ret = stm32mp1_set_clksrc(CLK_AXI_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001784 if (ret != 0) {
1785 return ret;
1786 }
Yann Gautiered342322019-02-15 17:33:27 +01001787 ret = stm32mp1_set_clksrc(CLK_MCU_HSI);
1788 if (ret != 0) {
1789 return ret;
1790 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001791
Yann Gautiere4a3c352019-02-14 10:53:33 +01001792 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) &
1793 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) {
1794 pll3_preserve = stm32mp1_check_pll_conf(_PLL3,
1795 clksrc[CLKSRC_PLL3],
1796 pllcfg[_PLL3],
1797 plloff[_PLL3]);
1798 pll4_preserve = stm32mp1_check_pll_conf(_PLL4,
1799 clksrc[CLKSRC_PLL4],
1800 pllcfg[_PLL4],
1801 plloff[_PLL4]);
1802 }
1803
Yann Gautier9aea69e2018-07-24 17:13:36 +02001804 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001805 if (((i == _PLL3) && pll3_preserve) ||
1806 ((i == _PLL4) && pll4_preserve)) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001807 continue;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001808 }
1809
1810 ret = stm32mp1_pll_stop(i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001811 if (ret != 0) {
1812 return ret;
1813 }
1814 }
1815
1816 /* Configure HSIDIV */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001817 if (stm32mp1_osc[_HSI] != 0U) {
1818 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001819 if (ret != 0) {
1820 return ret;
1821 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001822 stm32mp1_stgen_config();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001823 }
1824
1825 /* Select DIV */
1826 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001827 mmio_write_32(rcc_base + RCC_MPCKDIVR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001828 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001829 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001830 if (ret != 0) {
1831 return ret;
1832 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001833 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001834 if (ret != 0) {
1835 return ret;
1836 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001837 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001838 if (ret != 0) {
1839 return ret;
1840 }
Yann Gautiered342322019-02-15 17:33:27 +01001841 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR);
1842 if (ret != 0) {
1843 return ret;
1844 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001845 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001846 if (ret != 0) {
1847 return ret;
1848 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001849 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001850 if (ret != 0) {
1851 return ret;
1852 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001853 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001854 if (ret != 0) {
1855 return ret;
1856 }
1857
1858 /* No ready bit for RTC */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001859 mmio_write_32(rcc_base + RCC_RTCDIVR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001860 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK);
1861
1862 /* Configure PLLs source */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001863 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001864 if (ret != 0) {
1865 return ret;
1866 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001867
1868 if (!pll3_preserve) {
1869 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]);
1870 if (ret != 0) {
1871 return ret;
1872 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001873 }
1874
Yann Gautiere4a3c352019-02-14 10:53:33 +01001875 if (!pll4_preserve) {
1876 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]);
1877 if (ret != 0) {
1878 return ret;
1879 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001880 }
1881
1882 /* Configure and start PLLs */
1883 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1884 uint32_t fracv;
1885 uint32_t csg[PLLCSG_NB];
1886
Yann Gautiere4a3c352019-02-14 10:53:33 +01001887 if (((i == _PLL3) && pll3_preserve) ||
1888 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) {
1889 continue;
1890 }
1891
Yann Gautier9aea69e2018-07-24 17:13:36 +02001892 if (!fdt_check_node(plloff[i])) {
1893 continue;
1894 }
1895
Yann Gautiere4a3c352019-02-14 10:53:33 +01001896 if ((i == _PLL4) && pll4_bootrom) {
1897 /* Set output divider if not done by the Bootrom */
1898 stm32mp1_pll_config_output(i, pllcfg[i]);
1899 continue;
1900 }
1901
Andre Przywara2d5690c2020-03-26 11:50:33 +00001902 fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001903
Yann Gautiere4a3c352019-02-14 10:53:33 +01001904 ret = stm32mp1_pll_config(i, pllcfg[i], fracv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001905 if (ret != 0) {
1906 return ret;
1907 }
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001908 ret = fdt_read_uint32_array(fdt, plloff[i], "csg",
1909 (uint32_t)PLLCSG_NB, csg);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001910 if (ret == 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001911 stm32mp1_pll_csg(i, csg);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001912 } else if (ret != -FDT_ERR_NOTFOUND) {
1913 return ret;
1914 }
1915
Yann Gautiere4a3c352019-02-14 10:53:33 +01001916 stm32mp1_pll_start(i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001917 }
1918 /* Wait and start PLLs ouptut when ready */
1919 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1920 if (!fdt_check_node(plloff[i])) {
1921 continue;
1922 }
1923
Yann Gautiere4a3c352019-02-14 10:53:33 +01001924 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001925 if (ret != 0) {
1926 return ret;
1927 }
1928 }
1929 /* Wait LSE ready before to use it */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001930 if (stm32mp1_osc[_LSE] != 0U) {
1931 stm32mp1_lse_wait();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001932 }
1933
1934 /* Configure with expected clock source */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001935 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001936 if (ret != 0) {
1937 return ret;
1938 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001939 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001940 if (ret != 0) {
1941 return ret;
1942 }
Yann Gautiered342322019-02-15 17:33:27 +01001943 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]);
1944 if (ret != 0) {
1945 return ret;
1946 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001947 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001948
1949 /* Configure PKCK */
1950 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len);
1951 if (pkcs_cell != NULL) {
1952 bool ckper_disabled = false;
1953 uint32_t j;
1954
Yann Gautier9aea69e2018-07-24 17:13:36 +02001955 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) {
Yann Gautierf9af3bc2018-11-09 15:57:18 +01001956 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001957
1958 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) {
1959 ckper_disabled = true;
1960 continue;
1961 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001962 stm32mp1_pkcs_config(pkcs);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001963 }
1964
1965 /*
1966 * CKPER is source for some peripheral clocks
1967 * (FMC-NAND / QPSI-NOR) and switching source is allowed
1968 * only if previous clock is still ON
1969 * => deactivated CKPER only after switching clock
1970 */
1971 if (ckper_disabled) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001972 stm32mp1_pkcs_config(CLK_CKPER_DISABLED);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001973 }
1974 }
1975
1976 /* Switch OFF HSI if not found in device-tree */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001977 if (stm32mp1_osc[_HSI] == 0U) {
1978 stm32mp1_hsi_set(false);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001979 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001980 stm32mp1_stgen_config();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001981
1982 /* Software Self-Refresh mode (SSR) during DDR initilialization */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001983 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001984 RCC_DDRITFCR_DDRCKMOD_MASK,
1985 RCC_DDRITFCR_DDRCKMOD_SSR <<
1986 RCC_DDRITFCR_DDRCKMOD_SHIFT);
1987
1988 return 0;
1989}
1990
1991static void stm32mp1_osc_clk_init(const char *name,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001992 enum stm32mp_osc_id index)
1993{
1994 uint32_t frequency;
1995
Yann Gautiere4a3c352019-02-14 10:53:33 +01001996 if (fdt_osc_read_freq(name, &frequency) == 0) {
1997 stm32mp1_osc[index] = frequency;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001998 }
1999}
2000
2001static void stm32mp1_osc_init(void)
2002{
Yann Gautier9aea69e2018-07-24 17:13:36 +02002003 enum stm32mp_osc_id i;
2004
2005 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01002006 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002007 }
2008}
2009
Yann Gautierc7f9e962019-05-20 14:39:26 +02002010static void sync_earlyboot_clocks_state(void)
2011{
Etienne Carriere2a756c22019-12-08 08:23:35 +01002012 unsigned int idx;
2013 const unsigned long secure_enable[] = {
2014 AXIDCG,
2015 BSEC,
2016 DDRC1, DDRC1LP,
2017 DDRC2, DDRC2LP,
2018 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP,
2019 DDRPHYC, DDRPHYCLP,
2020 TZC1, TZC2,
2021 TZPC,
2022 STGEN_K,
2023 };
2024
2025 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) {
2026 stm32mp_clk_enable(secure_enable[idx]);
2027 }
2028
Yann Gautierc7f9e962019-05-20 14:39:26 +02002029 if (!stm32mp_is_single_core()) {
2030 stm32mp1_clk_enable_secure(RTCAPB);
2031 }
2032}
2033
Yann Gautier9aea69e2018-07-24 17:13:36 +02002034int stm32mp1_clk_probe(void)
2035{
Yann Gautier9aea69e2018-07-24 17:13:36 +02002036 stm32mp1_osc_init();
2037
Yann Gautierc7f9e962019-05-20 14:39:26 +02002038 sync_earlyboot_clocks_state();
2039
Yann Gautier9aea69e2018-07-24 17:13:36 +02002040 return 0;
2041}