Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / ee4be0fe0054828b0a1462c670bd1ccd2c866814 / . / bl32 / tsp / aarch64 / tsp_exceptions.S
blob: 96d958eb883bcb7b0627ef3c3827e0ae2a301e26 [file] [log] [blame]
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]1/*
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000[diff] [blame]2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]5 */
6
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]7#include <arch.h>
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]8#include <asm_macros.S>
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]9#include <bl_common.h>
10#include <tsp.h>
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]11
12
13 /* ----------------------------------------------------
14 * The caller-saved registers x0-x18 and LR are saved
15 * here.
16 * ----------------------------------------------------
17 */
18
19#define SCRATCH_REG_SIZE #(20 * 8)
20
21 .macro save_caller_regs_and_lr
22 sub sp, sp, SCRATCH_REG_SIZE
23 stp x0, x1, [sp]
24 stp x2, x3, [sp, #0x10]
25 stp x4, x5, [sp, #0x20]
26 stp x6, x7, [sp, #0x30]
27 stp x8, x9, [sp, #0x40]
28 stp x10, x11, [sp, #0x50]
29 stp x12, x13, [sp, #0x60]
30 stp x14, x15, [sp, #0x70]
31 stp x16, x17, [sp, #0x80]
32 stp x18, x30, [sp, #0x90]
33 .endm
34
35 .macro restore_caller_regs_and_lr
36 ldp x0, x1, [sp]
37 ldp x2, x3, [sp, #0x10]
38 ldp x4, x5, [sp, #0x20]
39 ldp x6, x7, [sp, #0x30]
40 ldp x8, x9, [sp, #0x40]
41 ldp x10, x11, [sp, #0x50]
42 ldp x12, x13, [sp, #0x60]
43 ldp x14, x15, [sp, #0x70]
44 ldp x16, x17, [sp, #0x80]
45 ldp x18, x30, [sp, #0x90]
46 add sp, sp, SCRATCH_REG_SIZE
47 .endm
48
Soby Mathewbec98512015-09-03 18:29:38 +0100[diff] [blame]49 /* ----------------------------------------------------
50 * Common TSP interrupt handling routine
51 * ----------------------------------------------------
52 */
53 .macro handle_tsp_interrupt label
54 /* Enable the SError interrupt */
55 msr daifclr, #DAIF_ABT_BIT
56
57 save_caller_regs_and_lr
58 bl tsp_common_int_handler
59 cbz x0, interrupt_exit_\label
60
61 /*
62 * This interrupt was not targetted to S-EL1 so send it to
63 * the monitor and wait for execution to resume.
64 */
65 smc #0
66interrupt_exit_\label:
67 restore_caller_regs_and_lr
68 eret
69 .endm
70
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]71 .globl tsp_exceptions
72
73 /* -----------------------------------------------------
74 * TSP exception handlers.
75 * -----------------------------------------------------
76 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]77vector_base tsp_exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]78 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]79 * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]80 * are expected and treated as irrecoverable errors.
81 * -----------------------------------------------------
82 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]83vector_entry sync_exception_sp_el0
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]84 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]85 check_vector_size sync_exception_sp_el0
86
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]87vector_entry irq_sp_el0
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]88 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]89 check_vector_size irq_sp_el0
90
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]91vector_entry fiq_sp_el0
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]92 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]93 check_vector_size fiq_sp_el0
94
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]95vector_entry serror_sp_el0
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]96 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]97 check_vector_size serror_sp_el0
98
99
100 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]101 * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]102 * are expected and handled
103 * -----------------------------------------------------
104 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]105vector_entry sync_exception_sp_elx
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]106 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]107 check_vector_size sync_exception_sp_elx
108
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]109vector_entry irq_sp_elx
Soby Mathewbec98512015-09-03 18:29:38 +0100[diff] [blame]110 handle_tsp_interrupt irq_sp_elx
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]111 check_vector_size irq_sp_elx
112
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]113vector_entry fiq_sp_elx
Soby Mathewbec98512015-09-03 18:29:38 +0100[diff] [blame]114 handle_tsp_interrupt fiq_sp_elx
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]115 check_vector_size fiq_sp_elx
116
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]117vector_entry serror_sp_elx
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]118 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]119 check_vector_size serror_sp_elx
120
121
122 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]123 * Lower EL using AArch64 : 0x400 - 0x600. No exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]124 * are handled since TSP does not implement a lower EL
125 * -----------------------------------------------------
126 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]127vector_entry sync_exception_aarch64
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]128 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]129 check_vector_size sync_exception_aarch64
130
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]131vector_entry irq_aarch64
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]132 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]133 check_vector_size irq_aarch64
134
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]135vector_entry fiq_aarch64
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]136 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]137 check_vector_size fiq_aarch64
138
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]139vector_entry serror_aarch64
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]140 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]141 check_vector_size serror_aarch64
142
143
144 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]145 * Lower EL using AArch32 : 0x600 - 0x800. No exceptions
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]146 * handled since the TSP does not implement a lower EL.
147 * -----------------------------------------------------
148 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]149vector_entry sync_exception_aarch32
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]150 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]151 check_vector_size sync_exception_aarch32
152
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]153vector_entry irq_aarch32
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]154 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]155 check_vector_size irq_aarch32
156
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]157vector_entry fiq_aarch32
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]158 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]159 check_vector_size fiq_aarch32
160
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100[diff] [blame]161vector_entry serror_aarch32
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000[diff] [blame]162 no_ret plat_panic_handler
Achin Guptaa4f50c22014-05-09 12:17:56 +0100[diff] [blame]163 check_vector_size serror_aarch32