Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 1f21bcf | 2016-02-01 13:57:25 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 32 | #include <asm_macros.S> |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 33 | #include <bl_common.h> |
| 34 | #include <tsp.h> |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 35 | |
| 36 | |
| 37 | /* ---------------------------------------------------- |
| 38 | * The caller-saved registers x0-x18 and LR are saved |
| 39 | * here. |
| 40 | * ---------------------------------------------------- |
| 41 | */ |
| 42 | |
| 43 | #define SCRATCH_REG_SIZE #(20 * 8) |
| 44 | |
| 45 | .macro save_caller_regs_and_lr |
| 46 | sub sp, sp, SCRATCH_REG_SIZE |
| 47 | stp x0, x1, [sp] |
| 48 | stp x2, x3, [sp, #0x10] |
| 49 | stp x4, x5, [sp, #0x20] |
| 50 | stp x6, x7, [sp, #0x30] |
| 51 | stp x8, x9, [sp, #0x40] |
| 52 | stp x10, x11, [sp, #0x50] |
| 53 | stp x12, x13, [sp, #0x60] |
| 54 | stp x14, x15, [sp, #0x70] |
| 55 | stp x16, x17, [sp, #0x80] |
| 56 | stp x18, x30, [sp, #0x90] |
| 57 | .endm |
| 58 | |
| 59 | .macro restore_caller_regs_and_lr |
| 60 | ldp x0, x1, [sp] |
| 61 | ldp x2, x3, [sp, #0x10] |
| 62 | ldp x4, x5, [sp, #0x20] |
| 63 | ldp x6, x7, [sp, #0x30] |
| 64 | ldp x8, x9, [sp, #0x40] |
| 65 | ldp x10, x11, [sp, #0x50] |
| 66 | ldp x12, x13, [sp, #0x60] |
| 67 | ldp x14, x15, [sp, #0x70] |
| 68 | ldp x16, x17, [sp, #0x80] |
| 69 | ldp x18, x30, [sp, #0x90] |
| 70 | add sp, sp, SCRATCH_REG_SIZE |
| 71 | .endm |
| 72 | |
Soby Mathew | bec9851 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 73 | /* ---------------------------------------------------- |
| 74 | * Common TSP interrupt handling routine |
| 75 | * ---------------------------------------------------- |
| 76 | */ |
| 77 | .macro handle_tsp_interrupt label |
| 78 | /* Enable the SError interrupt */ |
| 79 | msr daifclr, #DAIF_ABT_BIT |
| 80 | |
| 81 | save_caller_regs_and_lr |
| 82 | bl tsp_common_int_handler |
| 83 | cbz x0, interrupt_exit_\label |
| 84 | |
| 85 | /* |
| 86 | * This interrupt was not targetted to S-EL1 so send it to |
| 87 | * the monitor and wait for execution to resume. |
| 88 | */ |
| 89 | smc #0 |
| 90 | interrupt_exit_\label: |
| 91 | restore_caller_regs_and_lr |
| 92 | eret |
| 93 | .endm |
| 94 | |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 95 | .globl tsp_exceptions |
| 96 | |
| 97 | /* ----------------------------------------------------- |
| 98 | * TSP exception handlers. |
| 99 | * ----------------------------------------------------- |
| 100 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 101 | vector_base tsp_exceptions |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 102 | /* ----------------------------------------------------- |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 103 | * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 104 | * are expected and treated as irrecoverable errors. |
| 105 | * ----------------------------------------------------- |
| 106 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 107 | vector_entry sync_exception_sp_el0 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 108 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 109 | check_vector_size sync_exception_sp_el0 |
| 110 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 111 | vector_entry irq_sp_el0 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 112 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 113 | check_vector_size irq_sp_el0 |
| 114 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 115 | vector_entry fiq_sp_el0 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 116 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 117 | check_vector_size fiq_sp_el0 |
| 118 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 119 | vector_entry serror_sp_el0 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 120 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 121 | check_vector_size serror_sp_el0 |
| 122 | |
| 123 | |
| 124 | /* ----------------------------------------------------- |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 125 | * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 126 | * are expected and handled |
| 127 | * ----------------------------------------------------- |
| 128 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 129 | vector_entry sync_exception_sp_elx |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 130 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 131 | check_vector_size sync_exception_sp_elx |
| 132 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 133 | vector_entry irq_sp_elx |
Soby Mathew | bec9851 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 134 | handle_tsp_interrupt irq_sp_elx |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 135 | check_vector_size irq_sp_elx |
| 136 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 137 | vector_entry fiq_sp_elx |
Soby Mathew | bec9851 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 138 | handle_tsp_interrupt fiq_sp_elx |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 139 | check_vector_size fiq_sp_elx |
| 140 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 141 | vector_entry serror_sp_elx |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 142 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 143 | check_vector_size serror_sp_elx |
| 144 | |
| 145 | |
| 146 | /* ----------------------------------------------------- |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 147 | * Lower EL using AArch64 : 0x400 - 0x600. No exceptions |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 148 | * are handled since TSP does not implement a lower EL |
| 149 | * ----------------------------------------------------- |
| 150 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 151 | vector_entry sync_exception_aarch64 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 152 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 153 | check_vector_size sync_exception_aarch64 |
| 154 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 155 | vector_entry irq_aarch64 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 156 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 157 | check_vector_size irq_aarch64 |
| 158 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 159 | vector_entry fiq_aarch64 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 160 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 161 | check_vector_size fiq_aarch64 |
| 162 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 163 | vector_entry serror_aarch64 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 164 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 165 | check_vector_size serror_aarch64 |
| 166 | |
| 167 | |
| 168 | /* ----------------------------------------------------- |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 169 | * Lower EL using AArch32 : 0x600 - 0x800. No exceptions |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 170 | * handled since the TSP does not implement a lower EL. |
| 171 | * ----------------------------------------------------- |
| 172 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 173 | vector_entry sync_exception_aarch32 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 174 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 175 | check_vector_size sync_exception_aarch32 |
| 176 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 177 | vector_entry irq_aarch32 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 178 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 179 | check_vector_size irq_aarch32 |
| 180 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 181 | vector_entry fiq_aarch32 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 182 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 183 | check_vector_size fiq_aarch32 |
| 184 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 185 | vector_entry serror_aarch32 |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame^] | 186 | no_ret plat_panic_handler |
Achin Gupta | a4f50c2 | 2014-05-09 12:17:56 +0100 | [diff] [blame] | 187 | check_vector_size serror_aarch32 |