blob: 2db3b3467638231948754bda3cc282801b61cc6f [file] [log] [blame]
Achin Gupta7c88f3f2014-02-18 18:09:12 +00001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TSP_H__
32#define __TSP_H__
33
Achin Gupta7c88f3f2014-02-18 18:09:12 +000034/*
35 * SMC function IDs that TSP uses to signal various forms of completions
36 * to the secure payload dispatcher.
37 */
38#define TSP_ENTRY_DONE 0xf2000000
39#define TSP_ON_DONE 0xf2000001
40#define TSP_OFF_DONE 0xf2000002
41#define TSP_SUSPEND_DONE 0xf2000003
42#define TSP_RESUME_DONE 0xf2000004
Soby Mathew9f71f702014-05-09 20:49:17 +010043#define TSP_PREEMPTED 0xf2000005
Achin Gupta7c88f3f2014-02-18 18:09:12 +000044
Achin Gupta76717892014-05-09 11:42:56 +010045/*
46 * Function identifiers to handle FIQs through the synchronous handling model.
47 * If the TSP was previously interrupted then control has to be returned to
48 * the TSPD after handling the interrupt else execution can remain in the TSP.
49 */
50#define TSP_HANDLED_S_EL1_FIQ 0xf2000006
51#define TSP_EL3_FIQ 0xf2000007
Achin Gupta76717892014-05-09 11:42:56 +010052
53/* SMC function ID that TSP uses to request service from secure monitor */
Achin Gupta7c88f3f2014-02-18 18:09:12 +000054#define TSP_GET_ARGS 0xf2001000
55
Soby Mathew9f71f702014-05-09 20:49:17 +010056/*
57 * Identifiers for various TSP services. Corresponding function IDs (whether
58 * fast or standard) are generated by macros defined below
59 */
60#define TSP_ADD 0x2000
61#define TSP_SUB 0x2001
62#define TSP_MUL 0x2002
63#define TSP_DIV 0x2003
64#define TSP_HANDLE_FIQ_AND_RETURN 0x2004
65
66/*
67 * Generate function IDs for TSP services to be used in SMC calls, by
68 * appropriately setting bit 31 to differentiate standard and fast SMC calls
69 */
70#define TSP_STD_FID(fid) ((fid) | 0x72000000 | (0 << 31))
71#define TSP_FAST_FID(fid) ((fid) | 0x72000000 | (1 << 31))
72
73/* SMC function ID to request a previously preempted std smc */
74#define TSP_FID_RESUME TSP_STD_FID(0x3000)
75
76/*
77 * Identify a TSP service from function ID filtering the last 16 bits from the
78 * SMC function ID
79 */
80#define TSP_BARE_FID(fid) ((fid) & 0xffff)
Achin Gupta7c88f3f2014-02-18 18:09:12 +000081
Jeenu Viswambharandf1ddb52014-02-28 11:23:35 +000082/*
83 * Total number of function IDs implemented for services offered to NS clients.
84 * The function IDs are defined above
85 */
86#define TSP_NUM_FID 0x4
87
88/* TSP implementation version numbers */
89#define TSP_VERSION_MAJOR 0x0 /* Major version */
90#define TSP_VERSION_MINOR 0x1 /* Minor version */
91
92/*
93 * Standard Trusted OS Function IDs that fall under Trusted OS call range
94 * according to SMC calling convention
95 */
96#define TOS_CALL_COUNT 0xbf00ff00 /* Number of calls implemented */
97#define TOS_UID 0xbf00ff01 /* Implementation UID */
98/* 0xbf00ff02 is reserved */
99#define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */
100
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000101/* Definitions to help the assembler access the SMC/ERET args structure */
102#define TSP_ARGS_SIZE 0x40
103#define TSP_ARG0 0x0
104#define TSP_ARG1 0x8
105#define TSP_ARG2 0x10
106#define TSP_ARG3 0x18
107#define TSP_ARG4 0x20
108#define TSP_ARG5 0x28
109#define TSP_ARG6 0x30
110#define TSP_ARG7 0x38
111#define TSP_ARGS_END 0x40
112
113#ifndef __ASSEMBLY__
Dan Handley2bd4ef22014-04-09 13:14:54 +0100114
115#include <cassert.h>
Dan Handleyed6ff952014-05-14 17:44:19 +0100116#include <platform_def.h> /* For CACHE_WRITEBACK_GRANULE */
Achin Gupta76717892014-05-09 11:42:56 +0100117#include <spinlock.h>
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000118#include <stdint.h>
119
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100120typedef uint32_t tsp_vector_isn_t;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000121
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100122typedef struct tsp_vectors {
123 tsp_vector_isn_t std_smc_entry;
124 tsp_vector_isn_t fast_smc_entry;
125 tsp_vector_isn_t cpu_on_entry;
126 tsp_vector_isn_t cpu_off_entry;
127 tsp_vector_isn_t cpu_resume_entry;
128 tsp_vector_isn_t cpu_suspend_entry;
129 tsp_vector_isn_t fiq_entry;
130} tsp_vectors_t;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000131
Dan Handleye2712bc2014-04-10 15:37:22 +0100132typedef struct work_statistics {
Achin Gupta76717892014-05-09 11:42:56 +0100133 uint32_t fiq_count; /* Number of FIQs on this cpu */
Soby Mathew9f71f702014-05-09 20:49:17 +0100134 uint32_t irq_count; /* Number of IRQs on this cpu */
Achin Gupta76717892014-05-09 11:42:56 +0100135 uint32_t sync_fiq_count; /* Number of sync. fiqs on this cpu */
136 uint32_t sync_fiq_ret_count; /* Number of fiq returns on this cpu */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000137 uint32_t smc_count; /* Number of returns on this cpu */
138 uint32_t eret_count; /* Number of entries on this cpu */
139 uint32_t cpu_on_count; /* Number of cpu on requests */
140 uint32_t cpu_off_count; /* Number of cpu off requests */
141 uint32_t cpu_suspend_count; /* Number of cpu suspend requests */
142 uint32_t cpu_resume_count; /* Number of cpu resume requests */
Dan Handleye2712bc2014-04-10 15:37:22 +0100143} __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000144
Dan Handleye2712bc2014-04-10 15:37:22 +0100145typedef struct tsp_args {
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000146 uint64_t _regs[TSP_ARGS_END >> 3];
Dan Handleye2712bc2014-04-10 15:37:22 +0100147} __aligned(CACHE_WRITEBACK_GRANULE) tsp_args_t;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000148
149/* Macros to access members of the above structure using their offsets */
150#define read_sp_arg(args, offset) ((args)->_regs[offset >> 3])
Achin Gupta76717892014-05-09 11:42:56 +0100151#define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3]) \
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000152 = val)
153
154/*
155 * Ensure that the assembler's view of the size of the tsp_args is the
156 * same as the compilers
157 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100158CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000159
Dan Handleya17fefa2014-05-14 12:38:32 +0100160void tsp_get_magic(uint64_t args[4]);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000161
Dan Handleya17fefa2014-05-14 12:38:32 +0100162tsp_args_t *tsp_cpu_resume_main(uint64_t arg0,
163 uint64_t arg1,
164 uint64_t arg2,
165 uint64_t arg3,
166 uint64_t arg4,
167 uint64_t arg5,
168 uint64_t arg6,
169 uint64_t arg7);
170tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
171 uint64_t arg1,
172 uint64_t arg2,
173 uint64_t arg3,
174 uint64_t arg4,
175 uint64_t arg5,
176 uint64_t arg6,
177 uint64_t arg7);
178tsp_args_t *tsp_cpu_on_main(void);
179tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
180 uint64_t arg1,
181 uint64_t arg2,
182 uint64_t arg3,
183 uint64_t arg4,
184 uint64_t arg5,
185 uint64_t arg6,
186 uint64_t arg7);
Achin Gupta405406d2014-05-09 12:00:17 +0100187
188/* Generic Timer functions */
Dan Handleya17fefa2014-05-14 12:38:32 +0100189void tsp_generic_timer_start(void);
190void tsp_generic_timer_handler(void);
191void tsp_generic_timer_stop(void);
192void tsp_generic_timer_save(void);
193void tsp_generic_timer_restore(void);
Achin Gupta76717892014-05-09 11:42:56 +0100194
195/* FIQ management functions */
Dan Handleya17fefa2014-05-14 12:38:32 +0100196void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3);
Achin Gupta76717892014-05-09 11:42:56 +0100197
198/* Data structure to keep track of TSP statistics */
199extern spinlock_t console_lock;
200extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100201
202/* Vector table of jumps */
203extern tsp_vectors_t tsp_vector_table;
204
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000205#endif /* __ASSEMBLY__ */
206
207#endif /* __BL2_H__ */