Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 1 | /* |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <asm_macros.S> |
| 33 | #include <assert_macros.S> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 34 | #if IMAGE_BL31 |
| 35 | #include <cpu_data.h> |
| 36 | #endif |
David Cunado | 1f5f812 | 2017-01-17 14:40:15 +0000 | [diff] [blame] | 37 | #include <cpu_macros.S> |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 38 | #include <debug.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 39 | |
| 40 | /* Reset fn is needed in BL at reset vector */ |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 41 | #if IMAGE_BL1 || IMAGE_BL31 |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 42 | /* |
| 43 | * The reset handler common to all platforms. After a matching |
| 44 | * cpu_ops structure entry is found, the correponding reset_handler |
| 45 | * in the cpu_ops is invoked. |
Soby Mathew | b5a6304 | 2015-01-29 12:00:58 +0000 | [diff] [blame] | 46 | * Clobbers: x0 - x19, x30 |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 47 | */ |
| 48 | .globl reset_handler |
| 49 | func reset_handler |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 50 | mov x19, x30 |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 51 | |
Soby Mathew | b5a6304 | 2015-01-29 12:00:58 +0000 | [diff] [blame] | 52 | /* The plat_reset_handler can clobber x0 - x18, x30 */ |
Soby Mathew | f1785fd | 2014-08-14 12:22:32 +0100 | [diff] [blame] | 53 | bl plat_reset_handler |
| 54 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 55 | /* Get the matching cpu_ops pointer */ |
| 56 | bl get_cpu_ops_ptr |
| 57 | #if ASM_ASSERTION |
| 58 | cmp x0, #0 |
| 59 | ASM_ASSERT(ne) |
| 60 | #endif |
| 61 | |
| 62 | /* Get the cpu_ops reset handler */ |
| 63 | ldr x2, [x0, #CPU_RESET_FUNC] |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 64 | mov x30, x19 |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 65 | cbz x2, 1f |
Soby Mathew | b5a6304 | 2015-01-29 12:00:58 +0000 | [diff] [blame] | 66 | |
| 67 | /* The cpu_ops reset handler can clobber x0 - x19, x30 */ |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 68 | br x2 |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 69 | 1: |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 70 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 71 | endfunc reset_handler |
Soby Mathew | f1785fd | 2014-08-14 12:22:32 +0100 | [diff] [blame] | 72 | |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 73 | #endif /* IMAGE_BL1 || IMAGE_BL31 */ |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 74 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 75 | #if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ |
| 76 | /* |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 77 | * void prepare_cpu_pwr_dwn(unsigned int power_level) |
| 78 | * |
| 79 | * Prepare CPU power down function for all platforms. The function takes |
| 80 | * a domain level to be powered down as its parameter. After the cpu_ops |
| 81 | * pointer is retrieved from cpu_data, the handler for requested power |
| 82 | * level is called. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 83 | */ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 84 | .globl prepare_cpu_pwr_dwn |
| 85 | func prepare_cpu_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 86 | /* |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 87 | * If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the |
| 88 | * power down handler for the last power level |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 89 | */ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 90 | mov_imm x2, (CPU_MAX_PWR_DWN_OPS - 1) |
| 91 | cmp x0, x2 |
| 92 | csel x2, x2, x0, hi |
| 93 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 94 | mrs x1, tpidr_el3 |
| 95 | ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] |
| 96 | #if ASM_ASSERTION |
| 97 | cmp x0, #0 |
| 98 | ASM_ASSERT(ne) |
| 99 | #endif |
| 100 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 101 | /* Get the appropriate power down handler */ |
| 102 | mov x1, #CPU_PWR_DWN_OPS |
| 103 | add x1, x1, x2, lsl #3 |
| 104 | ldr x1, [x0, x1] |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 105 | br x1 |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 106 | endfunc prepare_cpu_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 107 | |
| 108 | |
| 109 | /* |
| 110 | * Initializes the cpu_ops_ptr if not already initialized |
Vikram Kanigiri | 9b38fc8 | 2015-01-29 18:27:38 +0000 | [diff] [blame] | 111 | * in cpu_data. This can be called without a runtime stack, but may |
| 112 | * only be called after the MMU is enabled. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 113 | * clobbers: x0 - x6, x10 |
| 114 | */ |
| 115 | .globl init_cpu_ops |
| 116 | func init_cpu_ops |
| 117 | mrs x6, tpidr_el3 |
| 118 | ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR] |
| 119 | cbnz x0, 1f |
| 120 | mov x10, x30 |
| 121 | bl get_cpu_ops_ptr |
| 122 | #if ASM_ASSERTION |
| 123 | cmp x0, #0 |
| 124 | ASM_ASSERT(ne) |
| 125 | #endif |
Soby Mathew | 7d861ea | 2014-11-18 10:14:14 +0000 | [diff] [blame] | 126 | str x0, [x6, #CPU_DATA_CPU_OPS_PTR]! |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 127 | mov x30, x10 |
| 128 | 1: |
| 129 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 130 | endfunc init_cpu_ops |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 131 | #endif /* IMAGE_BL31 */ |
| 132 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 133 | #if IMAGE_BL31 && CRASH_REPORTING |
| 134 | /* |
| 135 | * The cpu specific registers which need to be reported in a crash |
| 136 | * are reported via cpu_ops cpu_reg_dump function. After a matching |
| 137 | * cpu_ops structure entry is found, the correponding cpu_reg_dump |
| 138 | * in the cpu_ops is invoked. |
| 139 | */ |
| 140 | .globl do_cpu_reg_dump |
| 141 | func do_cpu_reg_dump |
| 142 | mov x16, x30 |
| 143 | |
| 144 | /* Get the matching cpu_ops pointer */ |
| 145 | bl get_cpu_ops_ptr |
| 146 | cbz x0, 1f |
| 147 | |
| 148 | /* Get the cpu_ops cpu_reg_dump */ |
| 149 | ldr x2, [x0, #CPU_REG_DUMP] |
| 150 | cbz x2, 1f |
| 151 | blr x2 |
| 152 | 1: |
| 153 | mov x30, x16 |
| 154 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 155 | endfunc do_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 156 | #endif |
| 157 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 158 | /* |
| 159 | * The below function returns the cpu_ops structure matching the |
| 160 | * midr of the core. It reads the MIDR_EL1 and finds the matching |
| 161 | * entry in cpu_ops entries. Only the implementation and part number |
| 162 | * are used to match the entries. |
| 163 | * Return : |
| 164 | * x0 - The matching cpu_ops pointer on Success |
| 165 | * x0 - 0 on failure. |
| 166 | * Clobbers : x0 - x5 |
| 167 | */ |
| 168 | .globl get_cpu_ops_ptr |
| 169 | func get_cpu_ops_ptr |
| 170 | /* Get the cpu_ops start and end locations */ |
| 171 | adr x4, (__CPU_OPS_START__ + CPU_MIDR) |
| 172 | adr x5, (__CPU_OPS_END__ + CPU_MIDR) |
| 173 | |
| 174 | /* Initialize the return parameter */ |
| 175 | mov x0, #0 |
| 176 | |
| 177 | /* Read the MIDR_EL1 */ |
| 178 | mrs x2, midr_el1 |
| 179 | mov_imm x3, CPU_IMPL_PN_MASK |
| 180 | |
| 181 | /* Retain only the implementation and part number using mask */ |
| 182 | and w2, w2, w3 |
| 183 | 1: |
| 184 | /* Check if we have reached end of list */ |
| 185 | cmp x4, x5 |
| 186 | b.eq error_exit |
| 187 | |
| 188 | /* load the midr from the cpu_ops */ |
| 189 | ldr x1, [x4], #CPU_OPS_SIZE |
| 190 | and w1, w1, w3 |
| 191 | |
| 192 | /* Check if midr matches to midr of this core */ |
| 193 | cmp w1, w2 |
| 194 | b.ne 1b |
| 195 | |
| 196 | /* Subtract the increment and offset to get the cpu-ops pointer */ |
| 197 | sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR) |
| 198 | error_exit: |
| 199 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 200 | endfunc get_cpu_ops_ptr |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 201 | |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 202 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
| 203 | .section .rodata.rev_verbose_str, "aS" |
| 204 | rev_verbose_str: |
| 205 | .asciz "VERBOSE: Skipping CPU specific reset operation for non-matching CPU revision number.\n" |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 206 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 207 | /* |
| 208 | * This function prints the above warning message to the crash console. |
| 209 | * It should be called when a CPU specific operation is enabled in the |
| 210 | * build but doesn't apply to this CPU revision/part number. |
| 211 | * |
| 212 | * Clobber: x30, x0 - x5 |
| 213 | */ |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 214 | .globl print_revision_warning |
| 215 | func print_revision_warning |
| 216 | mov x5, x30 |
| 217 | /* Ensure the console is initialized */ |
| 218 | bl plat_crash_console_init |
| 219 | /* Check if the console is initialized */ |
| 220 | cbz x0, 1f |
| 221 | /* The console is initialized */ |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 222 | adr x4, rev_verbose_str |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 223 | bl asm_print_str |
| 224 | 1: |
| 225 | ret x5 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 226 | endfunc print_revision_warning |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 227 | #endif |
| 228 | |