| Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <asm_macros.S> |
| 33 | #include <assert_macros.S> |
| 34 | #include <cpu_macros.S> |
| 35 | #if IMAGE_BL31 |
| 36 | #include <cpu_data.h> |
| 37 | #endif |
| 38 | |
| 39 | /* Reset fn is needed in BL at reset vector */ |
| 40 | #if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) |
| 41 | /* |
| 42 | * The reset handler common to all platforms. After a matching |
| 43 | * cpu_ops structure entry is found, the correponding reset_handler |
| 44 | * in the cpu_ops is invoked. |
| 45 | */ |
| 46 | .globl reset_handler |
| 47 | func reset_handler |
| 48 | mov x10, x30 |
| 49 | |
| 50 | /* Get the matching cpu_ops pointer */ |
| 51 | bl get_cpu_ops_ptr |
| 52 | #if ASM_ASSERTION |
| 53 | cmp x0, #0 |
| 54 | ASM_ASSERT(ne) |
| 55 | #endif |
| 56 | |
| 57 | /* Get the cpu_ops reset handler */ |
| 58 | ldr x2, [x0, #CPU_RESET_FUNC] |
| 59 | cbz x2, 1f |
| 60 | blr x2 |
| 61 | 1: |
| 62 | ret x10 |
| 63 | #endif /* IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) */ |
| 64 | |
| 65 | /* |
| 66 | * The below function returns the cpu_ops structure matching the |
| 67 | * midr of the core. It reads the MIDR_EL1 and finds the matching |
| 68 | * entry in cpu_ops entries. Only the implementation and part number |
| 69 | * are used to match the entries. |
| 70 | * Return : |
| 71 | * x0 - The matching cpu_ops pointer on Success |
| 72 | * x0 - 0 on failure. |
| 73 | * Clobbers : x0 - x5 |
| 74 | */ |
| 75 | .globl get_cpu_ops_ptr |
| 76 | func get_cpu_ops_ptr |
| 77 | /* Get the cpu_ops start and end locations */ |
| 78 | adr x4, (__CPU_OPS_START__ + CPU_MIDR) |
| 79 | adr x5, (__CPU_OPS_END__ + CPU_MIDR) |
| 80 | |
| 81 | /* Initialize the return parameter */ |
| 82 | mov x0, #0 |
| 83 | |
| 84 | /* Read the MIDR_EL1 */ |
| 85 | mrs x2, midr_el1 |
| 86 | mov_imm x3, CPU_IMPL_PN_MASK |
| 87 | |
| 88 | /* Retain only the implementation and part number using mask */ |
| 89 | and w2, w2, w3 |
| 90 | 1: |
| 91 | /* Check if we have reached end of list */ |
| 92 | cmp x4, x5 |
| 93 | b.eq error_exit |
| 94 | |
| 95 | /* load the midr from the cpu_ops */ |
| 96 | ldr x1, [x4], #CPU_OPS_SIZE |
| 97 | and w1, w1, w3 |
| 98 | |
| 99 | /* Check if midr matches to midr of this core */ |
| 100 | cmp w1, w2 |
| 101 | b.ne 1b |
| 102 | |
| 103 | /* Subtract the increment and offset to get the cpu-ops pointer */ |
| 104 | sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR) |
| 105 | error_exit: |
| 106 | ret |