Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __INTERRUPT_MGMT_H__ |
| 32 | #define __INTERRUPT_MGMT_H__ |
| 33 | |
| 34 | #include <arch.h> |
| 35 | |
| 36 | /******************************************************************************* |
| 37 | * Constants for the types of interrupts recognised by the IM framework |
| 38 | ******************************************************************************/ |
| 39 | #define INTR_TYPE_S_EL1 0 |
| 40 | #define INTR_TYPE_EL3 1 |
| 41 | #define INTR_TYPE_NS 2 |
| 42 | #define MAX_INTR_TYPES 3 |
| 43 | #define INTR_TYPE_INVAL MAX_INTR_TYPES |
| 44 | /* |
| 45 | * Constant passed to the interrupt handler in the 'id' field when the |
| 46 | * framework does not read the gic registers to determine the interrupt id. |
| 47 | */ |
| 48 | #define INTR_ID_UNAVAILABLE 0xFFFFFFFF |
| 49 | |
| 50 | |
| 51 | /******************************************************************************* |
| 52 | * Mask for _both_ the routing model bits in the 'flags' parameter and |
| 53 | * constants to define the valid routing models for each supported interrupt |
| 54 | * type |
| 55 | ******************************************************************************/ |
| 56 | #define INTR_RM_FLAGS_SHIFT 0x0 |
| 57 | #define INTR_RM_FLAGS_MASK 0x3 |
| 58 | /* Routed to EL3 from NS. Taken to S-EL1 from Secure */ |
| 59 | #define INTR_SEL1_VALID_RM0 0x2 |
| 60 | /* Routed to EL3 from NS and Secure */ |
| 61 | #define INTR_SEL1_VALID_RM1 0x3 |
| 62 | /* Routed to EL1/EL2 from NS and to S-EL1 from Secure */ |
| 63 | #define INTR_NS_VALID_RM0 0x0 |
| 64 | /* Routed to EL1/EL2 from NS and to EL3 from Secure */ |
| 65 | #define INTR_NS_VALID_RM1 0x1 |
Soby Mathew | 47903c0 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 66 | /* This is the default routing model */ |
| 67 | #define INTR_DEFAULT_RM 0x0 |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 68 | |
| 69 | /******************************************************************************* |
| 70 | * Constants for the _individual_ routing model bits in the 'flags' field for |
| 71 | * each interrupt type and mask to validate the 'flags' parameter while |
| 72 | * registering an interrupt handler |
| 73 | ******************************************************************************/ |
| 74 | #define INTR_TYPE_FLAGS_MASK 0xFFFFFFFC |
| 75 | |
| 76 | #define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */ |
| 77 | #define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */ |
| 78 | #define INTR_RM_FROM_FLAG_MASK 1 |
| 79 | #define get_interrupt_rm_flag(flag, ss) (((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \ |
| 80 | & INTR_RM_FROM_FLAG_MASK) |
| 81 | #define set_interrupt_rm_flag(flag, ss) (flag |= 1 << ss) |
| 82 | #define clr_interrupt_rm_flag(flag, ss) (flag &= ~(1 << ss)) |
| 83 | |
| 84 | |
| 85 | /******************************************************************************* |
| 86 | * Macros to validate the routing model bits in the 'flags' for a type |
| 87 | * of interrupt. If the model does not match one of the valid masks |
| 88 | * -EINVAL is returned. |
| 89 | ******************************************************************************/ |
| 90 | #define validate_sel1_interrupt_rm(x) (x == INTR_SEL1_VALID_RM0 ? 0 : \ |
| 91 | (x == INTR_SEL1_VALID_RM1 ? 0 :\ |
| 92 | -EINVAL)) |
| 93 | |
| 94 | #define validate_ns_interrupt_rm(x) (x == INTR_NS_VALID_RM0 ? 0 : \ |
| 95 | (x == INTR_NS_VALID_RM1 ? 0 :\ |
| 96 | -EINVAL)) |
| 97 | |
| 98 | /******************************************************************************* |
| 99 | * Macros to set the 'flags' parameter passed to an interrupt type handler. Only |
| 100 | * the flag to indicate the security state when the exception was generated is |
| 101 | * supported. |
| 102 | ******************************************************************************/ |
| 103 | #define INTR_SRC_SS_FLAG_SHIFT 0 /* BIT[0] */ |
| 104 | #define INTR_SRC_SS_FLAG_MASK 1 |
| 105 | #define set_interrupt_src_ss(flag, val) (flag |= val << INTR_SRC_SS_FLAG_SHIFT) |
| 106 | #define clr_interrupt_src_ss(flag) (flag &= ~(1 << INTR_SRC_SS_FLAG_SHIFT)) |
| 107 | #define get_interrupt_src_ss(flag) ((flag >> INTR_SRC_SS_FLAG_SHIFT) & \ |
| 108 | INTR_SRC_SS_FLAG_MASK) |
| 109 | |
| 110 | #ifndef __ASSEMBLY__ |
| 111 | |
| 112 | /* Prototype for defining a handler for an interrupt type */ |
| 113 | typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, |
| 114 | uint32_t flags, |
| 115 | void *handle, |
| 116 | void *cookie); |
| 117 | |
| 118 | /******************************************************************************* |
| 119 | * Function & variable prototypes |
| 120 | ******************************************************************************/ |
Dan Handley | a17fefa | 2014-05-14 12:38:32 +0100 | [diff] [blame] | 121 | uint32_t get_scr_el3_from_routing_model(uint32_t security_state); |
| 122 | int32_t set_routing_model(uint32_t type, uint32_t flags); |
| 123 | int32_t register_interrupt_type_handler(uint32_t type, |
| 124 | interrupt_type_handler_t handler, |
| 125 | uint32_t flags); |
| 126 | interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type); |
Soby Mathew | 47903c0 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 127 | int disable_intr_rm_local(uint32_t type, uint32_t security_state); |
| 128 | int enable_intr_rm_local(uint32_t type, uint32_t security_state); |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 129 | |
| 130 | #endif /*__ASSEMBLY__*/ |
| 131 | #endif /* __INTERRUPT_MGMT_H__ */ |