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git01.mediatek.com / filogic / atf / eb629496a8ebcd2cc6029927f80fa41dbf0879a4 / . / plat / mediatek / mt8188 / include / platform_def.h
blob: e72034c56c51c4889791d647b5f94694f7edb736 [file] [log] [blame]
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]1/*
developer33b70822022-09-07 18:30:05 +0800[diff] [blame]2 * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
developer3b31b932022-09-05 16:07:00 +0800[diff] [blame]10#include <arch_def.h>
11
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]12#define PLAT_PRIMARY_CPU (0x0)
13
14#define MT_GIC_BASE (0x0C000000)
15#define MCUCFG_BASE (0x0C530000)
developer768f1122022-09-16 11:30:43 +0800[diff] [blame]16#define MCUCFG_REG_SIZE (0x10000)
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]17#define IO_PHYS (0x10000000)
18
19/* Aggregate of all devices for MMU mapping */
20#define MTK_DEV_RNG0_BASE (MT_GIC_BASE)
21#define MTK_DEV_RNG0_SIZE (0x600000)
22#define MTK_DEV_RNG1_BASE (IO_PHYS)
23#define MTK_DEV_RNG1_SIZE (0x10000000)
24
developer33b70822022-09-07 18:30:05 +0800[diff] [blame]25#define TOPCKGEN_BASE (IO_PHYS)
26
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]27/*******************************************************************************
Chungying Lua566cc92023-03-15 14:16:28 +0800[diff] [blame]28 * APUSYS related constants
29 ******************************************************************************/
30#define BCRM_FMEM_PDN_BASE (IO_PHYS + 0x00276000)
Chungying Luf1f14b32023-03-15 15:31:56 +0800[diff] [blame]31#define APU_RCX_CONFIG (IO_PHYS + 0x09020000)
32#define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090e0000)
33#define APU_MBOX0 (IO_PHYS + 0x090e1000)
Karl Lieb629492023-04-27 14:00:10 +0800[diff] [blame^]34#define APU_MBOX1 (IO_PHYS + 0x090e2000)
Chungying Lua566cc92023-03-15 14:16:28 +0800[diff] [blame]35#define APU_RPCTOP (IO_PHYS + 0x090f0000)
36#define APU_PCUTOP (IO_PHYS + 0x090f1000)
37#define APU_AO_CTRL (IO_PHYS + 0x090f2000)
38#define APU_PLL (IO_PHYS + 0x090f3000)
39#define APU_ACC (IO_PHYS + 0x090f4000)
Karl Lidece5f02023-04-27 10:38:28 +0800[diff] [blame]40#define APU_SEC_CON (IO_PHYS + 0x090f5000)
Chungying Lua566cc92023-03-15 14:16:28 +0800[diff] [blame]41#define APU_ARETOP_ARE0 (IO_PHYS + 0x090f6000)
42#define APU_ARETOP_ARE1 (IO_PHYS + 0x090f7000)
43#define APU_ARETOP_ARE2 (IO_PHYS + 0x090f8000)
Karl Li130536e2023-04-21 11:43:24 +0800[diff] [blame]44#define APU_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090fc000)
Chungying Lua566cc92023-03-15 14:16:28 +0800[diff] [blame]45#define APU_ACX0_RPC_LITE (IO_PHYS + 0x09140000)
46#define BCRM_FMEM_PDN_SIZE (0x1000)
47
48/*******************************************************************************
developer369b0392022-09-20 14:50:36 +0800[diff] [blame]49 * AUDIO related constants
50 ******************************************************************************/
51#define AUDIO_BASE (IO_PHYS + 0x00b10000)
52
53/*******************************************************************************
54 * SPM related constants
55 ******************************************************************************/
56#define SPM_BASE (IO_PHYS + 0x00006000)
57
58/*******************************************************************************
Jianguo Zhangbe99c732022-07-29 13:55:03 +0800[diff] [blame]59 * GPIO related constants
60 ******************************************************************************/
61#define GPIO_BASE (IO_PHYS + 0x00005000)
Fengquan Chen67f11f02022-08-17 10:42:15 +0800[diff] [blame]62#define RGU_BASE (IO_PHYS + 0x00007000)
63#define DRM_BASE (IO_PHYS + 0x0000D000)
Jianguo Zhangbe99c732022-07-29 13:55:03 +0800[diff] [blame]64#define IOCFG_RM_BASE (IO_PHYS + 0x01C00000)
65#define IOCFG_LT_BASE (IO_PHYS + 0x01E10000)
66#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
67#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
68
69/*******************************************************************************
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]70 * UART related constants
71 ******************************************************************************/
72#define UART0_BASE (IO_PHYS + 0x01002000)
73#define UART_BAUDRATE (115200)
74
75/*******************************************************************************
Hui Liu39ea6142022-07-28 20:28:32 +0800[diff] [blame]76 * PMIC related constants
77 ******************************************************************************/
78#define PMIC_WRAP_BASE (IO_PHYS + 0x00024000)
79
80/*******************************************************************************
Chengci Xudb1e75b2022-07-20 16:20:15 +0800[diff] [blame]81 * Infra IOMMU related constants
82 ******************************************************************************/
developer33b70822022-09-07 18:30:05 +0800[diff] [blame]83#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
84#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00002000)
Chengci Xudb1e75b2022-07-20 16:20:15 +0800[diff] [blame]85#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
86#define PERICFG_AO_REG_SIZE (0x1000)
87
88/*******************************************************************************
developer66002552022-07-08 13:58:33 +0800[diff] [blame]89 * GIC-600 & interrupt handling related constants
90 ******************************************************************************/
91/* Base MTK_platform compatible GIC memory map */
92#define BASE_GICD_BASE (MT_GIC_BASE)
93#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
94
95/*******************************************************************************
developerbdeb0ba2022-07-08 14:48:56 +0800[diff] [blame]96 * CIRQ related constants
97 ******************************************************************************/
98#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
99#define MD_WDT_IRQ_BIT_ID (141)
100#define CIRQ_IRQ_NUM (730)
101#define CIRQ_REG_NUM (23)
102#define CIRQ_SPI_START (96)
103
104/*******************************************************************************
Chengci Xudb1e75b2022-07-20 16:20:15 +0800[diff] [blame]105 * MM IOMMU & SMI related constants
106 ******************************************************************************/
107#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000)
108#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000)
109#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000)
110#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000)
111#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000)
112#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000)
113#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000)
114#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000)
115#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000)
116#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000)
117#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000)
118#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000)
119#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000)
120#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000)
121#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000)
122#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000)
123#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000)
124#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000)
125#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000)
126#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000)
127#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000)
128#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000)
129#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000)
130#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000)
131#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000)
132#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000)
133#define SMI_LARB_REG_RNG_SIZE (0x1000)
134
135/*******************************************************************************
developer33b70822022-09-07 18:30:05 +0800[diff] [blame]136 * SPM related constants
137 ******************************************************************************/
138#define SPM_BASE (IO_PHYS + 0x00006000)
139
140/*******************************************************************************
141 * APMIXEDSYS related constants
142 ******************************************************************************/
143#define APMIXEDSYS (IO_PHYS + 0x0000C000)
144
145/*******************************************************************************
146 * VPPSYS related constants
147 ******************************************************************************/
148#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
149#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
150
151/*******************************************************************************
152 * VDOSYS related constants
153 ******************************************************************************/
154#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000)
155#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
156
157/*******************************************************************************
158 * SSPM_MBOX_3 related constants
159 ******************************************************************************/
160#define SSPM_MBOX_3_BASE (IO_PHYS + 0x00480000)
161
162/*******************************************************************************
developer7fa15de2022-07-11 19:03:35 +0800[diff] [blame]163 * DP related constants
164 ******************************************************************************/
165#define EDP_SEC_BASE (IO_PHYS + 0x0C504000)
166#define DP_SEC_BASE (IO_PHYS + 0x0C604000)
167#define EDP_SEC_SIZE (0x1000)
168#define DP_SEC_SIZE (0x1000)
169
170/*******************************************************************************
developer880fb172022-09-05 19:08:59 +0800[diff] [blame]171 * EMI MPU related constants
172 *******************************************************************************/
173#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
174#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000)
175
176/*******************************************************************************
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]177 * System counter frequency related constants
178 ******************************************************************************/
179#define SYS_COUNTER_FREQ_IN_HZ (13000000)
180#define SYS_COUNTER_FREQ_IN_MHZ (13)
181
182/*******************************************************************************
183 * Platform binary types for linking
184 ******************************************************************************/
185#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
186#define PLATFORM_LINKER_ARCH aarch64
187
188/*******************************************************************************
189 * Generic platform constants
190 ******************************************************************************/
191#define PLATFORM_STACK_SIZE (0x800)
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]192#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]193#define SOC_CHIP_ID U(0x8188)
194
195/*******************************************************************************
196 * Platform memory map related constants
197 ******************************************************************************/
198#define TZRAM_BASE (0x54600000)
developerb51d8ac2023-06-06 11:33:53 +0800[diff] [blame]199#define TZRAM_SIZE (0x00040000)
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]200
201/*******************************************************************************
202 * BL31 specific defines.
203 ******************************************************************************/
204/*
205 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
206 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
207 * little space for growth.
208 */
209#define BL31_BASE (TZRAM_BASE + 0x1000)
210#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
211
212/*******************************************************************************
213 * Platform specific page table and MMU setup constants
214 ******************************************************************************/
215#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
216#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
217#define MAX_XLAT_TABLES (16)
218#define MAX_MMAP_REGIONS (16)
219
developer1d69df52022-09-05 17:36:36 +0800[diff] [blame]220/*******************************************************************************
221 * CPU_EB TCM handling related constants
222 ******************************************************************************/
223#define CPU_EB_TCM_BASE (0x0C550000)
224#define CPU_EB_TCM_SIZE (0x10000)
225#define CPU_EB_MBOX3_OFFSET (0xFCE0)
226
227/*******************************************************************************
228 * CPU PM definitions
229 *******************************************************************************/
230#define PLAT_CPU_PM_B_BUCK_ISO_ID (6)
231#define PLAT_CPU_PM_ILDO_ID (6)
232#define CPU_IDLE_SRAM_BASE (0x11B000)
developer50c55f62022-11-11 09:51:51 +0800[diff] [blame]233#define CPU_IDLE_SRAM_SIZE (0x1000)
developer1d69df52022-09-05 17:36:36 +0800[diff] [blame]234
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]235#endif /* PLATFORM_DEF_H */