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git01.mediatek.com / filogic / atf / 130536eea011e87697aab911524adff8fe6f1562 / . / plat / mediatek / mt8188 / include / platform_def.h
blob: 7138c7a42e4a3a6944b1ca08aba5d5e110b2553d [file] [log] [blame]
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]1/*
developer33b70822022-09-07 18:30:05 +0800[diff] [blame]2 * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
developer3b31b932022-09-05 16:07:00 +0800[diff] [blame]10#include <arch_def.h>
11
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]12#define PLAT_PRIMARY_CPU (0x0)
13
14#define MT_GIC_BASE (0x0C000000)
15#define MCUCFG_BASE (0x0C530000)
developer768f1122022-09-16 11:30:43 +0800[diff] [blame]16#define MCUCFG_REG_SIZE (0x10000)
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]17#define IO_PHYS (0x10000000)
18
19/* Aggregate of all devices for MMU mapping */
20#define MTK_DEV_RNG0_BASE (MT_GIC_BASE)
21#define MTK_DEV_RNG0_SIZE (0x600000)
22#define MTK_DEV_RNG1_BASE (IO_PHYS)
23#define MTK_DEV_RNG1_SIZE (0x10000000)
24
developer33b70822022-09-07 18:30:05 +0800[diff] [blame]25#define TOPCKGEN_BASE (IO_PHYS)
26
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]27/*******************************************************************************
Chungying Lua566cc92023-03-15 14:16:28 +0800[diff] [blame]28 * APUSYS related constants
29 ******************************************************************************/
30#define BCRM_FMEM_PDN_BASE (IO_PHYS + 0x00276000)
Chungying Luf1f14b32023-03-15 15:31:56 +0800[diff] [blame]31#define APU_RCX_CONFIG (IO_PHYS + 0x09020000)
32#define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090e0000)
33#define APU_MBOX0 (IO_PHYS + 0x090e1000)
Chungying Lua566cc92023-03-15 14:16:28 +0800[diff] [blame]34#define APU_RPCTOP (IO_PHYS + 0x090f0000)
35#define APU_PCUTOP (IO_PHYS + 0x090f1000)
36#define APU_AO_CTRL (IO_PHYS + 0x090f2000)
37#define APU_PLL (IO_PHYS + 0x090f3000)
38#define APU_ACC (IO_PHYS + 0x090f4000)
39#define APU_ARETOP_ARE0 (IO_PHYS + 0x090f6000)
40#define APU_ARETOP_ARE1 (IO_PHYS + 0x090f7000)
41#define APU_ARETOP_ARE2 (IO_PHYS + 0x090f8000)
Karl Li130536e2023-04-21 11:43:24 +0800[diff] [blame^]42#define APU_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090fc000)
Chungying Lua566cc92023-03-15 14:16:28 +0800[diff] [blame]43#define APU_ACX0_RPC_LITE (IO_PHYS + 0x09140000)
44#define BCRM_FMEM_PDN_SIZE (0x1000)
45
46/*******************************************************************************
developer369b0392022-09-20 14:50:36 +0800[diff] [blame]47 * AUDIO related constants
48 ******************************************************************************/
49#define AUDIO_BASE (IO_PHYS + 0x00b10000)
50
51/*******************************************************************************
52 * SPM related constants
53 ******************************************************************************/
54#define SPM_BASE (IO_PHYS + 0x00006000)
55
56/*******************************************************************************
Jianguo Zhangbe99c732022-07-29 13:55:03 +0800[diff] [blame]57 * GPIO related constants
58 ******************************************************************************/
59#define GPIO_BASE (IO_PHYS + 0x00005000)
Fengquan Chen67f11f02022-08-17 10:42:15 +0800[diff] [blame]60#define RGU_BASE (IO_PHYS + 0x00007000)
61#define DRM_BASE (IO_PHYS + 0x0000D000)
Jianguo Zhangbe99c732022-07-29 13:55:03 +0800[diff] [blame]62#define IOCFG_RM_BASE (IO_PHYS + 0x01C00000)
63#define IOCFG_LT_BASE (IO_PHYS + 0x01E10000)
64#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
65#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
66
67/*******************************************************************************
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]68 * UART related constants
69 ******************************************************************************/
70#define UART0_BASE (IO_PHYS + 0x01002000)
71#define UART_BAUDRATE (115200)
72
73/*******************************************************************************
Hui Liu39ea6142022-07-28 20:28:32 +0800[diff] [blame]74 * PMIC related constants
75 ******************************************************************************/
76#define PMIC_WRAP_BASE (IO_PHYS + 0x00024000)
77
78/*******************************************************************************
Chengci Xudb1e75b2022-07-20 16:20:15 +0800[diff] [blame]79 * Infra IOMMU related constants
80 ******************************************************************************/
developer33b70822022-09-07 18:30:05 +0800[diff] [blame]81#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
82#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00002000)
Chengci Xudb1e75b2022-07-20 16:20:15 +0800[diff] [blame]83#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
84#define PERICFG_AO_REG_SIZE (0x1000)
85
86/*******************************************************************************
developer66002552022-07-08 13:58:33 +0800[diff] [blame]87 * GIC-600 & interrupt handling related constants
88 ******************************************************************************/
89/* Base MTK_platform compatible GIC memory map */
90#define BASE_GICD_BASE (MT_GIC_BASE)
91#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
92
93/*******************************************************************************
developerbdeb0ba2022-07-08 14:48:56 +0800[diff] [blame]94 * CIRQ related constants
95 ******************************************************************************/
96#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
97#define MD_WDT_IRQ_BIT_ID (141)
98#define CIRQ_IRQ_NUM (730)
99#define CIRQ_REG_NUM (23)
100#define CIRQ_SPI_START (96)
101
102/*******************************************************************************
Chengci Xudb1e75b2022-07-20 16:20:15 +0800[diff] [blame]103 * MM IOMMU & SMI related constants
104 ******************************************************************************/
105#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000)
106#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000)
107#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000)
108#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000)
109#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000)
110#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000)
111#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000)
112#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000)
113#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000)
114#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000)
115#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000)
116#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000)
117#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000)
118#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000)
119#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000)
120#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000)
121#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000)
122#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000)
123#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000)
124#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000)
125#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000)
126#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000)
127#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000)
128#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000)
129#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000)
130#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000)
131#define SMI_LARB_REG_RNG_SIZE (0x1000)
132
133/*******************************************************************************
developer33b70822022-09-07 18:30:05 +0800[diff] [blame]134 * SPM related constants
135 ******************************************************************************/
136#define SPM_BASE (IO_PHYS + 0x00006000)
137
138/*******************************************************************************
139 * APMIXEDSYS related constants
140 ******************************************************************************/
141#define APMIXEDSYS (IO_PHYS + 0x0000C000)
142
143/*******************************************************************************
144 * VPPSYS related constants
145 ******************************************************************************/
146#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
147#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
148
149/*******************************************************************************
150 * VDOSYS related constants
151 ******************************************************************************/
152#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000)
153#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
154
155/*******************************************************************************
156 * SSPM_MBOX_3 related constants
157 ******************************************************************************/
158#define SSPM_MBOX_3_BASE (IO_PHYS + 0x00480000)
159
160/*******************************************************************************
developer7fa15de2022-07-11 19:03:35 +0800[diff] [blame]161 * DP related constants
162 ******************************************************************************/
163#define EDP_SEC_BASE (IO_PHYS + 0x0C504000)
164#define DP_SEC_BASE (IO_PHYS + 0x0C604000)
165#define EDP_SEC_SIZE (0x1000)
166#define DP_SEC_SIZE (0x1000)
167
168/*******************************************************************************
developer880fb172022-09-05 19:08:59 +0800[diff] [blame]169 * EMI MPU related constants
170 *******************************************************************************/
171#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
172#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000)
173
174/*******************************************************************************
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]175 * System counter frequency related constants
176 ******************************************************************************/
177#define SYS_COUNTER_FREQ_IN_HZ (13000000)
178#define SYS_COUNTER_FREQ_IN_MHZ (13)
179
180/*******************************************************************************
181 * Platform binary types for linking
182 ******************************************************************************/
183#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
184#define PLATFORM_LINKER_ARCH aarch64
185
186/*******************************************************************************
187 * Generic platform constants
188 ******************************************************************************/
189#define PLATFORM_STACK_SIZE (0x800)
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]190#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]191#define SOC_CHIP_ID U(0x8188)
192
193/*******************************************************************************
194 * Platform memory map related constants
195 ******************************************************************************/
196#define TZRAM_BASE (0x54600000)
developerb51d8ac2023-06-06 11:33:53 +0800[diff] [blame]197#define TZRAM_SIZE (0x00040000)
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]198
199/*******************************************************************************
200 * BL31 specific defines.
201 ******************************************************************************/
202/*
203 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
204 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
205 * little space for growth.
206 */
207#define BL31_BASE (TZRAM_BASE + 0x1000)
208#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
209
210/*******************************************************************************
211 * Platform specific page table and MMU setup constants
212 ******************************************************************************/
213#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
214#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
215#define MAX_XLAT_TABLES (16)
216#define MAX_MMAP_REGIONS (16)
217
developer1d69df52022-09-05 17:36:36 +0800[diff] [blame]218/*******************************************************************************
219 * CPU_EB TCM handling related constants
220 ******************************************************************************/
221#define CPU_EB_TCM_BASE (0x0C550000)
222#define CPU_EB_TCM_SIZE (0x10000)
223#define CPU_EB_MBOX3_OFFSET (0xFCE0)
224
225/*******************************************************************************
226 * CPU PM definitions
227 *******************************************************************************/
228#define PLAT_CPU_PM_B_BUCK_ISO_ID (6)
229#define PLAT_CPU_PM_ILDO_ID (6)
230#define CPU_IDLE_SRAM_BASE (0x11B000)
developer50c55f62022-11-11 09:51:51 +0800[diff] [blame]231#define CPU_IDLE_SRAM_SIZE (0x1000)
developer1d69df52022-09-05 17:36:36 +0800[diff] [blame]232
developer6d207b42022-07-07 19:30:22 +0800[diff] [blame]233#endif /* PLATFORM_DEF_H */