Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | b9ae5db | 2018-05-02 11:23:56 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 10 | #include <cassert.h> |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 11 | #include <stdbool.h> |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 12 | #include <stdint.h> |
Isla Mitchell | c4a1a07 | 2017-08-07 11:20:13 +0100 | [diff] [blame] | 13 | #include <utils_def.h> |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 14 | #include <xlat_tables_v2.h> |
| 15 | #include "../xlat_tables_private.h" |
| 16 | |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 17 | /* |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 18 | * Returns true if the provided granule size is supported, false otherwise. |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 19 | */ |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 20 | bool xlat_arch_is_granule_size_supported(size_t size) |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 21 | { |
| 22 | u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); |
| 23 | |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 24 | if (size == PAGE_SIZE_4KB) { |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 25 | return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) & |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 26 | ID_AA64MMFR0_EL1_TGRAN4_MASK) == |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 27 | ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED; |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 28 | } else if (size == PAGE_SIZE_16KB) { |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 29 | return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) & |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 30 | ID_AA64MMFR0_EL1_TGRAN16_MASK) == |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 31 | ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED; |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 32 | } else if (size == PAGE_SIZE_64KB) { |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 33 | return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) & |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 34 | ID_AA64MMFR0_EL1_TGRAN64_MASK) == |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 35 | ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED; |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 36 | } else { |
| 37 | return 0; |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 38 | } |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 39 | } |
| 40 | |
| 41 | size_t xlat_arch_get_max_supported_granule_size(void) |
| 42 | { |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 43 | if (xlat_arch_is_granule_size_supported(PAGE_SIZE_64KB)) { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 44 | return PAGE_SIZE_64KB; |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 45 | } else if (xlat_arch_is_granule_size_supported(PAGE_SIZE_16KB)) { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 46 | return PAGE_SIZE_16KB; |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 47 | } else { |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 48 | assert(xlat_arch_is_granule_size_supported(PAGE_SIZE_4KB)); |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 49 | return PAGE_SIZE_4KB; |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 50 | } |
| 51 | } |
| 52 | |
Antonio Nino Diaz | bafc753 | 2017-10-25 11:53:25 +0100 | [diff] [blame] | 53 | unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 54 | { |
| 55 | /* Physical address can't exceed 48 bits */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 56 | assert((max_addr & ADDR_MASK_48_TO_63) == 0U); |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 57 | |
| 58 | /* 48 bits address */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 59 | if ((max_addr & ADDR_MASK_44_TO_47) != 0U) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 60 | return TCR_PS_BITS_256TB; |
| 61 | |
| 62 | /* 44 bits address */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 63 | if ((max_addr & ADDR_MASK_42_TO_43) != 0U) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 64 | return TCR_PS_BITS_16TB; |
| 65 | |
| 66 | /* 42 bits address */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 67 | if ((max_addr & ADDR_MASK_40_TO_41) != 0U) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 68 | return TCR_PS_BITS_4TB; |
| 69 | |
| 70 | /* 40 bits address */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 71 | if ((max_addr & ADDR_MASK_36_TO_39) != 0U) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 72 | return TCR_PS_BITS_1TB; |
| 73 | |
| 74 | /* 36 bits address */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 75 | if ((max_addr & ADDR_MASK_32_TO_35) != 0U) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 76 | return TCR_PS_BITS_64GB; |
| 77 | |
| 78 | return TCR_PS_BITS_4GB; |
| 79 | } |
| 80 | |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 81 | #if ENABLE_ASSERTIONS |
Antonio Nino Diaz | b9ae5db | 2018-05-02 11:23:56 +0100 | [diff] [blame] | 82 | /* |
| 83 | * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is |
| 84 | * supported in ARMv8.2 onwards. |
| 85 | */ |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 86 | static const unsigned int pa_range_bits_arr[] = { |
| 87 | PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, |
Antonio Nino Diaz | b9ae5db | 2018-05-02 11:23:56 +0100 | [diff] [blame] | 88 | PARANGE_0101, PARANGE_0110 |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 89 | }; |
| 90 | |
Sandrine Bailleux | c5b6377 | 2017-05-31 13:31:48 +0100 | [diff] [blame] | 91 | unsigned long long xlat_arch_get_max_supported_pa(void) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 92 | { |
| 93 | u_register_t pa_range = read_id_aa64mmfr0_el1() & |
| 94 | ID_AA64MMFR0_EL1_PARANGE_MASK; |
| 95 | |
| 96 | /* All other values are reserved */ |
| 97 | assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); |
| 98 | |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 99 | return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 100 | } |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 101 | #endif /* ENABLE_ASSERTIONS*/ |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 102 | |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 103 | bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 104 | { |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 105 | if (ctx->xlat_regime == EL1_EL0_REGIME) { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 106 | assert(xlat_arch_current_el() >= 1U); |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 107 | return (read_sctlr_el1() & SCTLR_M_BIT) != 0U; |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 108 | } else if (ctx->xlat_regime == EL2_REGIME) { |
| 109 | assert(xlat_arch_current_el() >= 2U); |
| 110 | return (read_sctlr_el2() & SCTLR_M_BIT) != 0U; |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 111 | } else { |
| 112 | assert(ctx->xlat_regime == EL3_REGIME); |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 113 | assert(xlat_arch_current_el() >= 3U); |
Antonio Nino Diaz | 5c97bd1 | 2018-08-02 09:57:29 +0100 | [diff] [blame] | 114 | return (read_sctlr_el3() & SCTLR_M_BIT) != 0U; |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 115 | } |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 116 | } |
| 117 | |
Antonio Nino Diaz | 37a5efa | 2018-08-07 12:47:12 +0100 | [diff] [blame] | 118 | bool is_dcache_enabled(void) |
| 119 | { |
| 120 | unsigned int el = (unsigned int)GET_EL(read_CurrentEl()); |
| 121 | |
| 122 | if (el == 1U) { |
| 123 | return (read_sctlr_el1() & SCTLR_C_BIT) != 0U; |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 124 | } else if (el == 2U) { |
| 125 | return (read_sctlr_el2() & SCTLR_C_BIT) != 0U; |
Antonio Nino Diaz | 37a5efa | 2018-08-07 12:47:12 +0100 | [diff] [blame] | 126 | } else { |
| 127 | return (read_sctlr_el3() & SCTLR_C_BIT) != 0U; |
| 128 | } |
| 129 | } |
| 130 | |
Antonio Nino Diaz | 44d3c21 | 2018-07-05 08:11:48 +0100 | [diff] [blame] | 131 | uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime) |
| 132 | { |
| 133 | if (xlat_regime == EL1_EL0_REGIME) { |
| 134 | return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN); |
| 135 | } else { |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 136 | assert((xlat_regime == EL2_REGIME) || |
| 137 | (xlat_regime == EL3_REGIME)); |
Antonio Nino Diaz | 44d3c21 | 2018-07-05 08:11:48 +0100 | [diff] [blame] | 138 | return UPPER_ATTRS(XN); |
| 139 | } |
| 140 | } |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 141 | |
Antonio Nino Diaz | ad5dc7f | 2018-07-11 09:46:45 +0100 | [diff] [blame] | 142 | void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime) |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 143 | { |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 144 | /* |
| 145 | * Ensure the translation table write has drained into memory before |
| 146 | * invalidating the TLB entry. |
| 147 | */ |
| 148 | dsbishst(); |
| 149 | |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 150 | /* |
| 151 | * This function only supports invalidation of TLB entries for the EL3 |
| 152 | * and EL1&0 translation regimes. |
| 153 | * |
| 154 | * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher |
| 155 | * exception level (see section D4.9.2 of the ARM ARM rev B.a). |
| 156 | */ |
| 157 | if (xlat_regime == EL1_EL0_REGIME) { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 158 | assert(xlat_arch_current_el() >= 1U); |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 159 | tlbivaae1is(TLBI_ADDR(va)); |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 160 | } else if (xlat_regime == EL2_REGIME) { |
| 161 | assert(xlat_arch_current_el() >= 2U); |
| 162 | tlbivae2is(TLBI_ADDR(va)); |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 163 | } else { |
| 164 | assert(xlat_regime == EL3_REGIME); |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 165 | assert(xlat_arch_current_el() >= 3U); |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 166 | tlbivae3is(TLBI_ADDR(va)); |
| 167 | } |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | void xlat_arch_tlbi_va_sync(void) |
| 171 | { |
| 172 | /* |
| 173 | * A TLB maintenance instruction can complete at any time after |
| 174 | * it is issued, but is only guaranteed to be complete after the |
| 175 | * execution of DSB by the PE that executed the TLB maintenance |
| 176 | * instruction. After the TLB invalidate instruction is |
| 177 | * complete, no new memory accesses using the invalidated TLB |
| 178 | * entries will be observed by any observer of the system |
| 179 | * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph |
| 180 | * "Ordering and completion of TLB maintenance instructions". |
| 181 | */ |
| 182 | dsbish(); |
| 183 | |
| 184 | /* |
| 185 | * The effects of a completed TLB maintenance instruction are |
| 186 | * only guaranteed to be visible on the PE that executed the |
| 187 | * instruction after the execution of an ISB instruction by the |
| 188 | * PE that executed the TLB maintenance instruction. |
| 189 | */ |
| 190 | isb(); |
| 191 | } |
| 192 | |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 193 | unsigned int xlat_arch_current_el(void) |
Antonio Nino Diaz | efabaa9 | 2017-04-27 13:30:22 +0100 | [diff] [blame] | 194 | { |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 195 | unsigned int el = (unsigned int)GET_EL(read_CurrentEl()); |
Antonio Nino Diaz | efabaa9 | 2017-04-27 13:30:22 +0100 | [diff] [blame] | 196 | |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 197 | assert(el > 0U); |
Antonio Nino Diaz | efabaa9 | 2017-04-27 13:30:22 +0100 | [diff] [blame] | 198 | |
| 199 | return el; |
| 200 | } |
| 201 | |
Antonio Nino Diaz | 67f799e | 2018-07-15 16:42:01 +0100 | [diff] [blame] | 202 | void setup_mmu_cfg(uint64_t *params, unsigned int flags, |
| 203 | const uint64_t *base_table, unsigned long long max_pa, |
| 204 | uintptr_t max_va, int xlat_regime) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 205 | { |
Antonio Nino Diaz | 668d9ee | 2018-07-12 15:44:42 +0100 | [diff] [blame] | 206 | uint64_t mair, ttbr0, tcr; |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 207 | uintptr_t virtual_addr_space_size; |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 208 | |
| 209 | /* Set attributes in the right indices of the MAIR. */ |
| 210 | mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); |
| 211 | mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); |
| 212 | mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); |
| 213 | |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 214 | /* |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 215 | * Limit the input address ranges and memory region sizes translated |
| 216 | * using TTBR0 to the given virtual address space size. |
| 217 | */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 218 | assert(max_va < ((uint64_t)UINTPTR_MAX)); |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 219 | |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 220 | virtual_addr_space_size = (uintptr_t)max_va + 1U; |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 221 | assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 222 | |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 223 | /* |
Sandrine Bailleux | 12e8644 | 2017-07-19 10:11:13 +0100 | [diff] [blame] | 224 | * __builtin_ctzll(0) is undefined but here we are guaranteed that |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 225 | * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. |
| 226 | */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 227 | int t0sz = 64 - __builtin_ctzll(virtual_addr_space_size); |
| 228 | |
| 229 | tcr = (uint64_t) t0sz; |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 230 | |
| 231 | /* |
| 232 | * Set the cacheability and shareability attributes for memory |
| 233 | * associated with translation table walks. |
| 234 | */ |
Antonio Nino Diaz | 50eb374 | 2018-07-24 10:20:53 +0100 | [diff] [blame] | 235 | if ((flags & XLAT_TABLE_NC) != 0U) { |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 236 | /* Inner & outer non-cacheable non-shareable. */ |
| 237 | tcr |= TCR_SH_NON_SHAREABLE | |
| 238 | TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; |
| 239 | } else { |
| 240 | /* Inner & outer WBWA & shareable. */ |
| 241 | tcr |= TCR_SH_INNER_SHAREABLE | |
| 242 | TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; |
| 243 | } |
| 244 | |
Sandrine Bailleux | c5b6377 | 2017-05-31 13:31:48 +0100 | [diff] [blame] | 245 | /* |
| 246 | * It is safer to restrict the max physical address accessible by the |
| 247 | * hardware as much as possible. |
| 248 | */ |
Antonio Nino Diaz | bafc753 | 2017-10-25 11:53:25 +0100 | [diff] [blame] | 249 | unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); |
Sandrine Bailleux | c5b6377 | 2017-05-31 13:31:48 +0100 | [diff] [blame] | 250 | |
Antonio Nino Diaz | 9d596c4 | 2018-07-12 15:43:07 +0100 | [diff] [blame] | 251 | if (xlat_regime == EL1_EL0_REGIME) { |
| 252 | /* |
| 253 | * TCR_EL1.EPD1: Disable translation table walk for addresses |
| 254 | * that are translated using TTBR1_EL1. |
| 255 | */ |
| 256 | tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 257 | } else if (xlat_regime == EL2_REGIME) { |
| 258 | tcr |= TCR_EL2_RES1 | (tcr_ps_bits << TCR_EL2_PS_SHIFT); |
Antonio Nino Diaz | 9d596c4 | 2018-07-12 15:43:07 +0100 | [diff] [blame] | 259 | } else { |
| 260 | assert(xlat_regime == EL3_REGIME); |
| 261 | tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); |
| 262 | } |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 263 | |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 264 | /* Set TTBR bits as well */ |
Antonio Nino Diaz | 668d9ee | 2018-07-12 15:44:42 +0100 | [diff] [blame] | 265 | ttbr0 = (uint64_t) base_table; |
| 266 | |
| 267 | #if ARM_ARCH_AT_LEAST(8, 2) |
| 268 | /* |
| 269 | * Enable CnP bit so as to share page tables with all PEs. This |
| 270 | * is mandatory for ARMv8.2 implementations. |
| 271 | */ |
| 272 | ttbr0 |= TTBR_CNP_BIT; |
| 273 | #endif |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 274 | |
Antonio Nino Diaz | 67f799e | 2018-07-15 16:42:01 +0100 | [diff] [blame] | 275 | params[MMU_CFG_MAIR] = mair; |
| 276 | params[MMU_CFG_TCR] = tcr; |
| 277 | params[MMU_CFG_TTBR0] = ttbr0; |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 278 | } |