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Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Jens Wiklander52c798e2015-12-07 14:37:10 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jens Wiklander52c798e2015-12-07 14:37:10 +01005 */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00006
Fu Weic2f78442017-05-27 21:21:42 +08007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
Jens Wiklander52c798e2015-12-07 14:37:10 +010010#include <libfdt.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
Jens Wiklander52c798e2015-12-07 14:37:10 +010012#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013
14#include <arch_helpers.h>
15#include <common/bl_common.h>
16#include <common/debug.h>
17#include <common/desc_image_load.h>
18#include <lib/optee_utils.h>
19#include <lib/utils.h>
20#include <plat/common/platform.h>
21
Isla Mitchelle3631462017-07-14 10:46:32 +010022#include "qemu_private.h"
Jens Wiklander52c798e2015-12-07 14:37:10 +010023
Jens Wiklander52c798e2015-12-07 14:37:10 +010024
Fu Weic2f78442017-05-27 21:21:42 +080025/* Data structure which holds the extents of the trusted SRAM for BL2 */
26static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
27
Jens Wiklandere22b91e2018-09-04 14:07:19 +020028void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
29 u_register_t arg2, u_register_t arg3)
Jens Wiklander52c798e2015-12-07 14:37:10 +010030{
Jens Wiklandere22b91e2018-09-04 14:07:19 +020031 meminfo_t *mem_layout = (void *)arg1;
32
Jens Wiklander52c798e2015-12-07 14:37:10 +010033 /* Initialize the console to provide early debug support */
Michalis Pappascca6cb72018-03-04 15:43:38 +080034 qemu_console_init();
Jens Wiklander52c798e2015-12-07 14:37:10 +010035
36 /* Setup the BL2 memory layout */
37 bl2_tzram_layout = *mem_layout;
38
39 plat_qemu_io_setup();
40}
41
42static void security_setup(void)
43{
44 /*
45 * This is where a TrustZone address space controller and other
46 * security related peripherals, would be configured.
47 */
48}
49
50static void update_dt(void)
51{
52 int ret;
53 void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE;
54
55 ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
56 if (ret < 0) {
57 ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
58 return;
59 }
60
61 if (dt_add_psci_node(fdt)) {
62 ERROR("Failed to add PSCI Device Tree node\n");
63 return;
64 }
65
66 if (dt_add_psci_cpu_enable_methods(fdt)) {
67 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
68 return;
69 }
70
71 ret = fdt_pack(fdt);
72 if (ret < 0)
73 ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
74}
75
76void bl2_platform_setup(void)
77{
78 security_setup();
79 update_dt();
80
81 /* TODO Initialize timer */
82}
83
Etienne Carriere911de8c2018-02-02 13:23:22 +010084#ifdef AARCH32
Antonio Nino Diaz099b0b12018-09-26 09:29:45 +010085#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
Etienne Carriere911de8c2018-02-02 13:23:22 +010086#else
87#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
88#endif
89
Jens Wiklander52c798e2015-12-07 14:37:10 +010090void bl2_plat_arch_setup(void)
91{
Etienne Carriere911de8c2018-02-02 13:23:22 +010092 QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base,
Jens Wiklander52c798e2015-12-07 14:37:10 +010093 bl2_tzram_layout.total_size,
Michalis Pappasba861122018-02-28 14:36:03 +080094 BL_CODE_BASE, BL_CODE_END,
95 BL_RO_DATA_BASE, BL_RO_DATA_END,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +090096 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
Jens Wiklander52c798e2015-12-07 14:37:10 +010097}
98
99/*******************************************************************************
100 * Gets SPSR for BL32 entry
101 ******************************************************************************/
102static uint32_t qemu_get_spsr_for_bl32_entry(void)
103{
Etienne Carriere911de8c2018-02-02 13:23:22 +0100104#ifdef AARCH64
Jens Wiklander52c798e2015-12-07 14:37:10 +0100105 /*
106 * The Secure Payload Dispatcher service is responsible for
107 * setting the SPSR prior to entry into the BL3-2 image.
108 */
109 return 0;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100110#else
111 return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
112 DISABLE_ALL_EXCEPTIONS);
113#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +0100114}
115
116/*******************************************************************************
117 * Gets SPSR for BL33 entry
118 ******************************************************************************/
119static uint32_t qemu_get_spsr_for_bl33_entry(void)
120{
Jens Wiklander52c798e2015-12-07 14:37:10 +0100121 uint32_t spsr;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100122#ifdef AARCH64
123 unsigned int mode;
Jens Wiklander52c798e2015-12-07 14:37:10 +0100124
125 /* Figure out what mode we enter the non-secure world in */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000126 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
Jens Wiklander52c798e2015-12-07 14:37:10 +0100127
128 /*
129 * TODO: Consider the possibility of specifying the SPSR in
130 * the FIP ToC and allowing the platform to have a say as
131 * well.
132 */
133 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
Etienne Carriere911de8c2018-02-02 13:23:22 +0100134#else
135 spsr = SPSR_MODE32(MODE32_svc,
136 plat_get_ns_image_entrypoint() & 0x1,
137 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
138#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +0100139 return spsr;
140}
141
Fu Weic2f78442017-05-27 21:21:42 +0800142static int qemu_bl2_handle_post_image_load(unsigned int image_id)
143{
144 int err = 0;
145 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Etienne Carriere911de8c2018-02-02 13:23:22 +0100146#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200147 bl_mem_params_node_t *pager_mem_params = NULL;
148 bl_mem_params_node_t *paged_mem_params = NULL;
149#endif
Fu Weic2f78442017-05-27 21:21:42 +0800150
151 assert(bl_mem_params);
152
153 switch (image_id) {
Fu Weic2f78442017-05-27 21:21:42 +0800154 case BL32_IMAGE_ID:
Etienne Carriere911de8c2018-02-02 13:23:22 +0100155#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200156 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
157 assert(pager_mem_params);
158
159 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
160 assert(paged_mem_params);
161
162 err = parse_optee_header(&bl_mem_params->ep_info,
163 &pager_mem_params->image_info,
164 &paged_mem_params->image_info);
165 if (err != 0) {
166 WARN("OPTEE header parse error.\n");
167 }
168
Etienne Carriere911de8c2018-02-02 13:23:22 +0100169#if defined(SPD_opteed)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200170 /*
171 * OP-TEE expect to receive DTB address in x2.
172 * This will be copied into x2 by dispatcher.
173 */
174 bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100175#else /* case AARCH32_SP_OPTEE */
176 bl_mem_params->ep_info.args.arg0 =
177 bl_mem_params->ep_info.args.arg1;
178 bl_mem_params->ep_info.args.arg1 = 0;
179 bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE;
180 bl_mem_params->ep_info.args.arg3 = 0;
181#endif
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200182#endif
Fu Weic2f78442017-05-27 21:21:42 +0800183 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
184 break;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100185
Fu Weic2f78442017-05-27 21:21:42 +0800186 case BL33_IMAGE_ID:
Etienne Carriere911de8c2018-02-02 13:23:22 +0100187#ifdef AARCH32_SP_OPTEE
188 /* AArch32 only core: OP-TEE expects NSec EP in register LR */
189 pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
190 assert(pager_mem_params);
191 pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
192#endif
193
Fu Weic2f78442017-05-27 21:21:42 +0800194 /* BL33 expects to receive the primary CPU MPID (through r0) */
195 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
196 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
197 break;
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000198 default:
199 /* Do nothing in default case */
200 break;
Fu Weic2f78442017-05-27 21:21:42 +0800201 }
202
203 return err;
204}
205
206/*******************************************************************************
207 * This function can be used by the platforms to update/use image
208 * information for given `image_id`.
209 ******************************************************************************/
210int bl2_plat_handle_post_image_load(unsigned int image_id)
211{
212 return qemu_bl2_handle_post_image_load(image_id);
213}
Jens Wiklander52c798e2015-12-07 14:37:10 +0100214
Etienne Carriere911de8c2018-02-02 13:23:22 +0100215uintptr_t plat_get_ns_image_entrypoint(void)
Jens Wiklander52c798e2015-12-07 14:37:10 +0100216{
217 return NS_IMAGE_OFFSET;
218}