blob: a3dfa1e1d306bdb48c358178c2ac4dc7d3c08d70 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Daniel Boulby45a2c9e2018-07-06 16:54:44 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Dan Handley9df48042015-03-19 18:58:55 +00009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <bl32/tsp/platform_tsp.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <drivers/arm/pl011.h>
15#include <drivers/console.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000016#include <plat/arm/common/plat_arm.h>
Dan Handley9df48042015-03-19 18:58:55 +000017
Dan Handley9df48042015-03-19 18:58:55 +000018/* Weak definitions may be overridden in specific ARM standard platform */
19#pragma weak tsp_early_platform_setup
20#pragma weak tsp_platform_setup
21#pragma weak tsp_plat_arch_setup
22
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010023#define MAP_BL_TSP_TOTAL MAP_REGION_FLAT( \
24 BL32_BASE, \
25 BL32_END - BL32_BASE, \
26 MT_MEMORY | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +000027
28/*******************************************************************************
29 * Initialize the UART
30 ******************************************************************************/
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010031#if MULTI_CONSOLE_API
32static console_pl011_t arm_tsp_runtime_console;
33#endif
34
Dan Handley9df48042015-03-19 18:58:55 +000035void arm_tsp_early_platform_setup(void)
36{
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010037#if MULTI_CONSOLE_API
Dan Handley9df48042015-03-19 18:58:55 +000038 /*
39 * Initialize a different console than already in use to display
40 * messages from TSP
41 */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010042 int rc = console_pl011_register(PLAT_ARM_TSP_UART_BASE,
43 PLAT_ARM_TSP_UART_CLK_IN_HZ,
44 ARM_CONSOLE_BAUDRATE,
45 &arm_tsp_runtime_console);
46 if (rc == 0)
47 panic();
48
49 console_set_scope(&arm_tsp_runtime_console.console,
50 CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
51#else
Dan Handley9df48042015-03-19 18:58:55 +000052 console_init(PLAT_ARM_TSP_UART_BASE, PLAT_ARM_TSP_UART_CLK_IN_HZ,
53 ARM_CONSOLE_BAUDRATE);
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010054#endif /* MULTI_CONSOLE_API */
Dan Handley9df48042015-03-19 18:58:55 +000055}
56
57void tsp_early_platform_setup(void)
58{
59 arm_tsp_early_platform_setup();
60}
61
62/*******************************************************************************
63 * Perform platform specific setup placeholder
64 ******************************************************************************/
65void tsp_platform_setup(void)
66{
Achin Gupta1fa7eb62015-11-03 14:18:34 +000067 plat_arm_gic_driver_init();
Dan Handley9df48042015-03-19 18:58:55 +000068}
69
70/*******************************************************************************
71 * Perform the very early platform specific architectural setup here. At the
72 * moment this is only intializes the MMU
73 ******************************************************************************/
74void tsp_plat_arch_setup(void)
75{
Dan Handley9df48042015-03-19 18:58:55 +000076#if USE_COHERENT_MEM
Paul Beesley1fbc97b2019-01-11 18:26:51 +000077 /* Ensure ARM platforms don't use coherent memory in TSP */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010078 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +000079#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010080
81 const mmap_region_t bl_regions[] = {
82 MAP_BL_TSP_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +010083 ARM_MAP_BL_RO,
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010084 {0}
85 };
86
Roberto Vargas344ff022018-10-19 16:44:18 +010087 setup_page_tables(bl_regions, plat_arm_get_mmap());
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010088 enable_mmu_el1(0);
Dan Handley9df48042015-03-19 18:58:55 +000089}