Rework page table setup for varying number of mem regions
Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their coherent memory region doesn't contain anything and
therefore has a size of 0. Add check to ensure this
doesn't change without us knowing.
Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index 16125ad..491705d 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -5,6 +5,7 @@
*/
#include <arm_def.h>
+#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
@@ -20,6 +21,10 @@
#pragma weak tsp_platform_setup
#pragma weak tsp_plat_arch_setup
+#define MAP_BL_TSP_TOTAL MAP_REGION_FLAT( \
+ BL32_BASE, \
+ BL32_END - BL32_BASE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
/*******************************************************************************
* Initialize the UART
@@ -69,16 +74,18 @@
******************************************************************************/
void tsp_plat_arch_setup(void)
{
- arm_setup_page_tables(BL32_BASE,
- (BL32_END - BL32_BASE),
- BL_CODE_BASE,
- BL_CODE_END,
- BL_RO_DATA_BASE,
- BL_RO_DATA_END
#if USE_COHERENT_MEM
- , BL_COHERENT_RAM_BASE,
- BL_COHERENT_RAM_END
+ /* Ensure ARM platforms dont use coherent memory in TSP */
+ assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
#endif
- );
+
+ const mmap_region_t bl_regions[] = {
+ MAP_BL_TSP_TOTAL,
+ ARM_MAP_BL_CODE,
+ ARM_MAP_BL_RO_DATA,
+ {0}
+ };
+
+ arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
enable_mmu_el1(0);
}