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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handley2b6b5742015-03-19 19:17:53 +00002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000032#include <asm_macros.S>
Soby Mathew12012dd2015-10-26 14:01:53 +000033#include <gicv2.h>
34#include <gicv3.h>
Dan Handley4fd2f5c2014-08-04 11:41:20 +010035#include <platform_def.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000036#include <v2m_def.h>
Vikram Kanigiri96377452014-04-24 11:02:16 +010037#include "../drivers/pwrc/fvp_pwrc.h"
Dan Handley2b6b5742015-03-19 19:17:53 +000038#include "../fvp_def.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010039
Vikram Kanigiri96377452014-04-24 11:02:16 +010040 .globl plat_secondary_cold_boot_setup
Soby Mathewfec4eb72015-07-01 16:16:20 +010041 .globl plat_get_my_entrypoint
Soby Mathewfec4eb72015-07-01 16:16:20 +010042 .globl plat_is_my_cpu_primary
Achin Gupta4f6ad662013-10-25 09:08:21 +010043
Dan Handleyea451572014-05-15 14:53:30 +010044 .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
Dan Handley2b6b5742015-03-19 19:17:53 +000045 ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID
Vikram Kanigiri96377452014-04-24 11:02:16 +010046 ldr \w_tmp, [\x_tmp]
Dan Handley2b6b5742015-03-19 19:17:53 +000047 ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
Vikram Kanigiri96377452014-04-24 11:02:16 +010048 cmp \w_tmp, #BLD_GIC_VE_MMAP
49 csel \res, \param1, \param2, eq
50 .endm
51
52 /* -----------------------------------------------------
53 * void plat_secondary_cold_boot_setup (void);
54 *
55 * This function performs any platform specific actions
56 * needed for a secondary cpu after a cold reset e.g
57 * mark the cpu's presence, mechanism to place it in a
58 * holding pen etc.
59 * TODO: Should we read the PSYS register to make sure
60 * that the request has gone through.
61 * -----------------------------------------------------
62 */
63func plat_secondary_cold_boot_setup
Sandrine Bailleuxd47c9a52015-10-02 14:35:25 +010064#ifndef EL3_PAYLOAD_BASE
Vikram Kanigiri96377452014-04-24 11:02:16 +010065 /* ---------------------------------------------
66 * Power down this cpu.
67 * TODO: Do we need to worry about powering the
68 * cluster down as well here. That will need
69 * locks which we won't have unless an elf-
70 * loader zeroes out the zi section.
71 * ---------------------------------------------
72 */
73 mrs x0, mpidr_el1
74 ldr x1, =PWRC_BASE
75 str w0, [x1, #PPOFFR_OFF]
76
77 /* ---------------------------------------------
Soby Mathew12012dd2015-10-26 14:01:53 +000078 * Disable GIC bypass as well
Vikram Kanigiri96377452014-04-24 11:02:16 +010079 * ---------------------------------------------
80 */
Soby Mathew12012dd2015-10-26 14:01:53 +000081 /* Check for GICv3 system register access */
82 mrs x0, id_aa64pfr0_el1
83 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
84 cmp x0, #1
85 b.ne gicv2_bypass_disable
86
87 /* Check for SRE enable */
88 mrs x1, ICC_SRE_EL3
89 tst x1, #ICC_SRE_SRE_BIT
90 b.eq gicv2_bypass_disable
91
92 mrs x2, ICC_SRE_EL3
93 orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)
94 msr ICC_SRE_EL3, x2
95 b secondary_cold_boot_wait
96
97gicv2_bypass_disable:
Vikram Kanigiri96377452014-04-24 11:02:16 +010098 ldr x0, =VE_GICC_BASE
99 ldr x1, =BASE_GICC_BASE
Dan Handleyea451572014-05-15 14:53:30 +0100100 fvp_choose_gicmmap x0, x1, x2, w2, x1
Vikram Kanigiri96377452014-04-24 11:02:16 +0100101 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
102 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
103 str w0, [x1, #GICC_CTLR]
104
Soby Mathew12012dd2015-10-26 14:01:53 +0000105secondary_cold_boot_wait:
Vikram Kanigiri96377452014-04-24 11:02:16 +0100106 /* ---------------------------------------------
107 * There is no sane reason to come out of this
108 * wfi so panic if we do. This cpu will be pow-
109 * ered on and reset by the cpu_on pm api
110 * ---------------------------------------------
111 */
112 dsb sy
113 wfi
114cb_panic:
115 b cb_panic
Sandrine Bailleuxd47c9a52015-10-02 14:35:25 +0100116#else
117 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
118
119 /* Wait until the entrypoint gets populated */
120poll_mailbox:
121 ldr x1, [x0]
122 cbz x1, 1f
123 br x1
1241:
125 wfe
126 b poll_mailbox
127#endif /* EL3_PAYLOAD_BASE */
Kévin Petita877c252015-03-24 14:03:57 +0000128endfunc plat_secondary_cold_boot_setup
Vikram Kanigiri96377452014-04-24 11:02:16 +0100129
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100130 /* ---------------------------------------------------------------------
Soby Mathewfec4eb72015-07-01 16:16:20 +0100131 * unsigned long plat_get_my_entrypoint (void);
Vikram Kanigiri96377452014-04-24 11:02:16 +0100132 *
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100133 * Main job of this routine is to distinguish between a cold and warm
134 * boot. On FVP, this information can be queried from the power
135 * controller. The Power Control SYS Status Register (PSYSR) indicates
136 * the wake-up reason for the CPU.
137 *
138 * For a cold boot, return 0.
139 * For a warm boot, read the mailbox and return the address it contains.
Vikram Kanigiri96377452014-04-24 11:02:16 +0100140 *
Vikram Kanigiri96377452014-04-24 11:02:16 +0100141 * TODO: PSYSR is a common register and should be
142 * accessed using locks. Since its not possible
143 * to use locks immediately after a cold reset
144 * we are relying on the fact that after a cold
145 * reset all cpus will read the same WK field
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100146 * ---------------------------------------------------------------------
Vikram Kanigiri96377452014-04-24 11:02:16 +0100147 */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100148func plat_get_my_entrypoint
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100149 /* ---------------------------------------------------------------------
150 * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
151 * WakeRequest signal" then it is a warm boot.
152 * ---------------------------------------------------------------------
153 */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100154 mrs x2, mpidr_el1
Vikram Kanigiri96377452014-04-24 11:02:16 +0100155 ldr x1, =PWRC_BASE
156 str w2, [x1, #PSYSR_OFF]
157 ldr w2, [x1, #PSYSR_OFF]
Soby Mathew2ae23192015-04-30 12:27:41 +0100158 ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
Juan Castillo9a5b56e2014-07-11 10:23:18 +0100159 cmp w2, #WKUP_PPONR
160 beq warm_reset
161 cmp w2, #WKUP_GICREQ
162 beq warm_reset
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100163
164 /* Cold reset */
Juan Castillo9a5b56e2014-07-11 10:23:18 +0100165 mov x0, #0
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100166 ret
167
Vikram Kanigiri96377452014-04-24 11:02:16 +0100168warm_reset:
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100169 /* ---------------------------------------------------------------------
170 * A mailbox is maintained in the trusted SRAM. It is flushed out of the
171 * caches after every update using normal memory so it is safe to read
172 * it here with SO attributes.
173 * ---------------------------------------------------------------------
Vikram Kanigiri96377452014-04-24 11:02:16 +0100174 */
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100175 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100176 ldr x0, [x0]
Vikram Kanigiri96377452014-04-24 11:02:16 +0100177 cbz x0, _panic
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100178 ret
179
180 /* ---------------------------------------------------------------------
181 * The power controller indicates this is a warm reset but the mailbox
182 * is empty. This should never happen!
183 * ---------------------------------------------------------------------
184 */
185_panic:
186 b _panic
Soby Mathewfec4eb72015-07-01 16:16:20 +0100187endfunc plat_get_my_entrypoint
Vikram Kanigiri96377452014-04-24 11:02:16 +0100188
Soby Matheweb3bbf12015-06-08 12:32:50 +0100189 /* -----------------------------------------------------
190 * unsigned int plat_is_my_cpu_primary (void);
191 *
192 * Find out whether the current cpu is the primary
193 * cpu.
194 * -----------------------------------------------------
195 */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100196func plat_is_my_cpu_primary
197 mrs x0, mpidr_el1
Juan Castillob3dbeb02014-07-16 15:53:43 +0100198 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
199 cmp x0, #FVP_PRIMARY_CPU
Soby Matheweb3bbf12015-06-08 12:32:50 +0100200 cset w0, eq
Juan Castillob3dbeb02014-07-16 15:53:43 +0100201 ret
Soby Mathewfec4eb72015-07-01 16:16:20 +0100202endfunc plat_is_my_cpu_primary