Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 1 | /* |
Harvey Hsieh | b9b374f | 2016-11-15 22:04:51 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | d292e5d | 2018-05-17 10:42:18 -0700 | [diff] [blame] | 3 | * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 8 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <string.h> |
| 10 | |
| 11 | #include <arch_helpers.h> |
| 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <lib/mmio.h> |
| 15 | #include <lib/utils.h> |
| 16 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 17 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 18 | #include <mce.h> |
| 19 | #include <memctrl.h> |
| 20 | #include <memctrl_v2.h> |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 21 | #include <smmu.h> |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 22 | #include <tegra_def.h> |
Varun Wadekar | e81177d | 2016-07-18 17:43:41 -0700 | [diff] [blame] | 23 | #include <tegra_platform.h> |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 24 | |
| 25 | /* Video Memory base and size (live values) */ |
| 26 | static uint64_t video_mem_base; |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 27 | static uint64_t video_mem_size_mb; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 28 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 29 | /* |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 30 | * Init Memory controller during boot. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 31 | */ |
| 32 | void tegra_memctrl_setup(void) |
| 33 | { |
| 34 | uint32_t val; |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 35 | const uint32_t *mc_streamid_override_regs; |
| 36 | uint32_t num_streamid_override_regs; |
| 37 | const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs; |
| 38 | uint32_t num_streamid_sec_cfgs; |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 39 | const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 40 | uint32_t i; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 41 | |
| 42 | INFO("Tegra Memory Controller (v2)\n"); |
| 43 | |
| 44 | /* Program the SMMU pagesize */ |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 45 | tegra_smmu_init(); |
Varun Wadekar | cba0529 | 2017-11-29 17:14:24 -0800 | [diff] [blame] | 46 | |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 47 | /* Get the settings from the platform */ |
Anthony Zhou | 4408e88 | 2017-07-07 14:29:51 +0800 | [diff] [blame] | 48 | assert(plat_mc_settings != NULL); |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 49 | mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg; |
| 50 | num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs; |
| 51 | mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg; |
| 52 | num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 53 | |
| 54 | /* Program all the Stream ID overrides */ |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 55 | for (i = 0; i < num_streamid_override_regs; i++) |
| 56 | tegra_mc_streamid_write_32(mc_streamid_override_regs[i], |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 57 | MC_STREAM_ID_MAX); |
| 58 | |
| 59 | /* Program the security config settings for all Stream IDs */ |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 60 | for (i = 0; i < num_streamid_sec_cfgs; i++) { |
| 61 | val = mc_streamid_sec_cfgs[i].override_enable << 16 | |
| 62 | mc_streamid_sec_cfgs[i].override_client_inputs << 8 | |
| 63 | mc_streamid_sec_cfgs[i].override_client_ns_flag << 0; |
| 64 | tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | /* |
| 68 | * All requests at boot time, and certain requests during |
| 69 | * normal run time, are physically addressed and must bypass |
| 70 | * the SMMU. The client hub logic implements a hardware bypass |
| 71 | * path around the Translation Buffer Units (TBU). During |
| 72 | * boot-time, the SMMU_BYPASS_CTRL register (which defaults to |
| 73 | * TBU_BYPASS mode) will be used to steer all requests around |
| 74 | * the uninitialized TBUs. During normal operation, this register |
| 75 | * is locked into TBU_BYPASS_SID config, which routes requests |
| 76 | * with special StreamID 0x7f on the bypass path and all others |
| 77 | * through the selected TBU. This is done to disable SMMU Bypass |
| 78 | * mode, as it could be used to circumvent SMMU security checks. |
| 79 | */ |
| 80 | tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG, |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 81 | MC_SMMU_BYPASS_CONFIG_SETTINGS); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 82 | |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 83 | /* |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 84 | * Re-configure MSS to allow ROC to deal with ordering of the |
| 85 | * Memory Controller traffic. This is needed as the Memory Controller |
| 86 | * boots with MSS having all control, but ROC provides a performance |
| 87 | * boost as compared to MSS. |
| 88 | */ |
Puneet Saxena | cf8c0e2 | 2017-08-04 17:19:55 +0530 | [diff] [blame] | 89 | if (plat_mc_settings->reconfig_mss_clients != NULL) { |
| 90 | plat_mc_settings->reconfig_mss_clients(); |
| 91 | } |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 92 | |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 93 | /* Program overrides for MC transactions */ |
Puneet Saxena | cf8c0e2 | 2017-08-04 17:19:55 +0530 | [diff] [blame] | 94 | if (plat_mc_settings->set_txn_overrides != NULL) { |
| 95 | plat_mc_settings->set_txn_overrides(); |
| 96 | } |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 97 | } |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 98 | |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 99 | /* |
| 100 | * Restore Memory Controller settings after "System Suspend" |
| 101 | */ |
| 102 | void tegra_memctrl_restore_settings(void) |
| 103 | { |
Puneet Saxena | cf8c0e2 | 2017-08-04 17:19:55 +0530 | [diff] [blame] | 104 | const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); |
| 105 | |
| 106 | assert(plat_mc_settings != NULL); |
| 107 | |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 108 | /* |
| 109 | * Re-configure MSS to allow ROC to deal with ordering of the |
| 110 | * Memory Controller traffic. This is needed as the Memory Controller |
| 111 | * resets during System Suspend with MSS having all control, but ROC |
| 112 | * provides a performance boost as compared to MSS. |
| 113 | */ |
Puneet Saxena | cf8c0e2 | 2017-08-04 17:19:55 +0530 | [diff] [blame] | 114 | if (plat_mc_settings->reconfig_mss_clients != NULL) { |
| 115 | plat_mc_settings->reconfig_mss_clients(); |
| 116 | } |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 117 | |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 118 | /* Program overrides for MC transactions */ |
Puneet Saxena | cf8c0e2 | 2017-08-04 17:19:55 +0530 | [diff] [blame] | 119 | if (plat_mc_settings->set_txn_overrides != NULL) { |
| 120 | plat_mc_settings->set_txn_overrides(); |
| 121 | } |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 122 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 123 | /* video memory carveout region */ |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 124 | if (video_mem_base != 0ULL) { |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 125 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, |
| 126 | (uint32_t)video_mem_base); |
| 127 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 128 | (uint32_t)(video_mem_base >> 32)); |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 129 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 130 | |
| 131 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 132 | * MCE propagates the VideoMem configuration values across the |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 133 | * CCPLEX. |
| 134 | */ |
| 135 | mce_update_gsc_videomem(); |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | /* |
| 140 | * Secure the BL31 DRAM aperture. |
| 141 | * |
| 142 | * phys_base = physical base of TZDRAM aperture |
| 143 | * size_in_bytes = size of aperture in bytes |
| 144 | */ |
| 145 | void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 146 | { |
| 147 | /* |
Varun Wadekar | f3cd509 | 2017-10-30 14:35:17 -0700 | [diff] [blame] | 148 | * Perform platform specific steps. |
Harvey Hsieh | c95802d | 2016-07-29 20:10:59 +0800 | [diff] [blame] | 149 | */ |
Varun Wadekar | f3cd509 | 2017-10-30 14:35:17 -0700 | [diff] [blame] | 150 | plat_memctrl_tzdram_setup(phys_base, size_in_bytes); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | /* |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 154 | * Secure the BL31 TZRAM aperture. |
| 155 | * |
| 156 | * phys_base = physical base of TZRAM aperture |
| 157 | * size_in_bytes = size of aperture in bytes |
| 158 | */ |
| 159 | void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 160 | { |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 161 | uint32_t index; |
| 162 | uint32_t total_128kb_blocks = size_in_bytes >> 17; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 163 | uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 164 | uint32_t val; |
| 165 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 166 | INFO("Configuring TrustZone SRAM Memory Carveout\n"); |
| 167 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 168 | /* |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 169 | * Reset the access configuration registers to restrict access |
| 170 | * to the TZRAM aperture |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 171 | */ |
Steven Kao | b688d38 | 2017-09-06 13:32:21 +0800 | [diff] [blame] | 172 | for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 173 | index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); |
| 174 | index += 4U) { |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 175 | tegra_mc_write_32(index, 0); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 176 | } |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 177 | |
| 178 | /* |
Steven Kao | b688d38 | 2017-09-06 13:32:21 +0800 | [diff] [blame] | 179 | * Enable CPU access configuration registers to access the TZRAM aperture |
| 180 | */ |
| 181 | if (!tegra_chipid_is_t186()) { |
| 182 | val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0); |
| 183 | val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW; |
| 184 | tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val); |
| 185 | } |
| 186 | |
| 187 | /* |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 188 | * Set the TZRAM base. TZRAM base must be 4k aligned, at least. |
| 189 | */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 190 | assert((phys_base & (uint64_t)0xFFF) == 0U); |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 191 | tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base); |
| 192 | tegra_mc_write_32(MC_TZRAM_BASE_HI, |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 193 | (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 194 | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 195 | /* |
| 196 | * Set the TZRAM size |
| 197 | * |
| 198 | * total size = (number of 128KB blocks) + (number of remaining 4KB |
| 199 | * blocks) |
| 200 | * |
| 201 | */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 202 | val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 203 | total_128kb_blocks; |
| 204 | tegra_mc_write_32(MC_TZRAM_SIZE, val); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 205 | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 206 | /* |
| 207 | * Lock the configuration settings by disabling TZ-only lock |
| 208 | * and locking the configuration against any future changes |
| 209 | * at all. |
| 210 | */ |
| 211 | val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG); |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 212 | val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 213 | val |= MC_GSC_LOCK_CFG_SETTINGS_BIT; |
Steven Kao | b688d38 | 2017-09-06 13:32:21 +0800 | [diff] [blame] | 214 | if (!tegra_chipid_is_t186()) { |
| 215 | val |= MC_GSC_ENABLE_CPU_SECURE_BIT; |
| 216 | } |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 217 | tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 218 | |
| 219 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 220 | * MCE propagates the security configuration values across the |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 221 | * CCPLEX. |
| 222 | */ |
| 223 | mce_update_gsc_tzram(); |
| 224 | } |
| 225 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 226 | static void tegra_lock_videomem_nonoverlap(uint64_t phys_base, |
| 227 | uint64_t size_in_bytes) |
| 228 | { |
| 229 | uint32_t index; |
| 230 | uint64_t total_128kb_blocks = size_in_bytes >> 17; |
| 231 | uint64_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; |
| 232 | uint64_t val; |
| 233 | |
| 234 | /* |
| 235 | * Reset the access configuration registers to restrict access to |
| 236 | * old Videomem aperture |
| 237 | */ |
| 238 | for (index = MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0; |
| 239 | index < ((uint32_t)MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); |
| 240 | index += 4U) { |
| 241 | tegra_mc_write_32(index, 0); |
| 242 | } |
| 243 | |
| 244 | /* |
| 245 | * Set the base. It must be 4k aligned, at least. |
| 246 | */ |
| 247 | assert((phys_base & (uint64_t)0xFFF) == 0U); |
| 248 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, (uint32_t)phys_base); |
| 249 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, |
| 250 | (uint32_t)(phys_base >> 32) & (uint32_t)MC_GSC_BASE_HI_MASK); |
| 251 | |
| 252 | /* |
| 253 | * Set the aperture size |
| 254 | * |
| 255 | * total size = (number of 128KB blocks) + (number of remaining 4KB |
| 256 | * blocks) |
| 257 | * |
| 258 | */ |
| 259 | val = (uint32_t)((residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | |
| 260 | total_128kb_blocks); |
| 261 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, (uint32_t)val); |
| 262 | |
| 263 | /* |
| 264 | * Lock the configuration settings by enabling TZ-only lock and |
| 265 | * locking the configuration against any future changes from NS |
| 266 | * world. |
| 267 | */ |
| 268 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_CFG, |
| 269 | (uint32_t)MC_GSC_ENABLE_TZ_LOCK_BIT); |
| 270 | |
| 271 | /* |
| 272 | * MCE propagates the GSC configuration values across the |
| 273 | * CCPLEX. |
| 274 | */ |
| 275 | } |
| 276 | |
| 277 | static void tegra_unlock_videomem_nonoverlap(void) |
| 278 | { |
| 279 | /* Clear the base */ |
| 280 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, 0); |
| 281 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, 0); |
| 282 | |
| 283 | /* Clear the size */ |
| 284 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, 0); |
| 285 | } |
| 286 | |
| 287 | static void tegra_clear_videomem(uintptr_t non_overlap_area_start, |
| 288 | unsigned long long non_overlap_area_size) |
| 289 | { |
Varun Wadekar | 117a2e0 | 2017-08-03 11:40:34 -0700 | [diff] [blame] | 290 | int ret; |
| 291 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 292 | /* |
| 293 | * Map the NS memory first, clean it and then unmap it. |
| 294 | */ |
Varun Wadekar | 117a2e0 | 2017-08-03 11:40:34 -0700 | [diff] [blame] | 295 | ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 296 | non_overlap_area_start, /* VA */ |
| 297 | non_overlap_area_size, /* size */ |
| 298 | MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ |
Varun Wadekar | 117a2e0 | 2017-08-03 11:40:34 -0700 | [diff] [blame] | 299 | assert(ret == 0); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 300 | |
| 301 | zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size); |
| 302 | flush_dcache_range(non_overlap_area_start, non_overlap_area_size); |
| 303 | |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 304 | (void)mmap_remove_dynamic_region(non_overlap_area_start, |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 305 | non_overlap_area_size); |
| 306 | } |
| 307 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 308 | /* |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 309 | * Program the Video Memory carveout region |
| 310 | * |
| 311 | * phys_base = physical base of aperture |
| 312 | * size_in_bytes = size of aperture in bytes |
| 313 | */ |
| 314 | void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 315 | { |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 316 | uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20); |
| 317 | uintptr_t vmem_end_new = phys_base + size_in_bytes; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 318 | unsigned long long non_overlap_area_size; |
Varun Wadekar | e60f1bf | 2016-02-17 10:10:50 -0800 | [diff] [blame] | 319 | |
| 320 | /* |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 321 | * Setup the Memory controller to restrict CPU accesses to the Video |
| 322 | * Memory region |
| 323 | */ |
| 324 | INFO("Configuring Video Memory Carveout\n"); |
| 325 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 326 | /* |
| 327 | * Configure Memory Controller directly for the first time. |
| 328 | */ |
| 329 | if (video_mem_base == 0U) |
| 330 | goto done; |
| 331 | |
| 332 | /* |
| 333 | * Lock the non overlapping memory being cleared so that other masters |
| 334 | * do not accidently write to it. The memory would be unlocked once |
| 335 | * the non overlapping region is cleared and the new memory |
| 336 | * settings take effect. |
| 337 | */ |
| 338 | tegra_lock_videomem_nonoverlap(video_mem_base, |
| 339 | video_mem_size_mb << 20); |
| 340 | |
| 341 | /* |
| 342 | * Clear the old regions now being exposed. The following cases |
| 343 | * can occur - |
| 344 | * |
| 345 | * 1. clear whole old region (no overlap with new region) |
| 346 | * 2. clear old sub-region below new base |
| 347 | * 3. clear old sub-region above new end |
| 348 | */ |
| 349 | INFO("Cleaning previous Video Memory Carveout\n"); |
| 350 | |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 351 | if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) { |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 352 | tegra_clear_videomem(video_mem_base, |
Varun Wadekar | 8b1c004 | 2019-09-05 08:17:02 -0700 | [diff] [blame] | 353 | video_mem_size_mb << 20U); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 354 | } else { |
| 355 | if (video_mem_base < phys_base) { |
| 356 | non_overlap_area_size = phys_base - video_mem_base; |
Varun Wadekar | 8b1c004 | 2019-09-05 08:17:02 -0700 | [diff] [blame] | 357 | tegra_clear_videomem(video_mem_base, non_overlap_area_size); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 358 | } |
| 359 | if (vmem_end_old > vmem_end_new) { |
| 360 | non_overlap_area_size = vmem_end_old - vmem_end_new; |
Varun Wadekar | 8b1c004 | 2019-09-05 08:17:02 -0700 | [diff] [blame] | 361 | tegra_clear_videomem(vmem_end_new, non_overlap_area_size); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 362 | } |
| 363 | } |
| 364 | |
| 365 | done: |
| 366 | /* program the Videomem aperture */ |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 367 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); |
| 368 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 369 | (uint32_t)(phys_base >> 32)); |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 370 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 371 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 372 | /* unlock the previous locked nonoverlapping aperture */ |
| 373 | tegra_unlock_videomem_nonoverlap(); |
| 374 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 375 | /* store new values */ |
| 376 | video_mem_base = phys_base; |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 377 | video_mem_size_mb = size_in_bytes >> 20; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 378 | |
| 379 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 380 | * MCE propagates the VideoMem configuration values across the |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 381 | * CCPLEX. |
| 382 | */ |
| 383 | mce_update_gsc_videomem(); |
| 384 | } |
Varun Wadekar | c92050b | 2017-03-29 14:57:29 -0700 | [diff] [blame] | 385 | |
| 386 | /* |
| 387 | * This feature exists only for v1 of the Tegra Memory Controller. |
| 388 | */ |
| 389 | void tegra_memctrl_disable_ahb_redirection(void) |
| 390 | { |
| 391 | ; /* do nothing */ |
| 392 | } |
Harvey Hsieh | 359be95 | 2017-08-21 15:01:53 +0800 | [diff] [blame] | 393 | |
| 394 | void tegra_memctrl_clear_pending_interrupts(void) |
| 395 | { |
| 396 | ; /* do nothing */ |
| 397 | } |