Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | f4194ee | 2018-01-10 15:00:20 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __INTERRUPT_MGMT_H__ |
| 8 | #define __INTERRUPT_MGMT_H__ |
| 9 | |
| 10 | #include <arch.h> |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * Constants for the types of interrupts recognised by the IM framework |
| 14 | ******************************************************************************/ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 15 | #define INTR_TYPE_S_EL1 U(0) |
| 16 | #define INTR_TYPE_EL3 U(1) |
| 17 | #define INTR_TYPE_NS U(2) |
| 18 | #define MAX_INTR_TYPES U(3) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 19 | #define INTR_TYPE_INVAL MAX_INTR_TYPES |
Jeenu Viswambharan | dce70b3 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 20 | |
| 21 | /* Interrupt routing modes */ |
| 22 | #define INTR_ROUTING_MODE_PE 0 |
| 23 | #define INTR_ROUTING_MODE_ANY 1 |
| 24 | |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 25 | /* |
| 26 | * Constant passed to the interrupt handler in the 'id' field when the |
| 27 | * framework does not read the gic registers to determine the interrupt id. |
| 28 | */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 29 | #define INTR_ID_UNAVAILABLE U(0xFFFFFFFF) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 30 | |
| 31 | |
| 32 | /******************************************************************************* |
| 33 | * Mask for _both_ the routing model bits in the 'flags' parameter and |
| 34 | * constants to define the valid routing models for each supported interrupt |
| 35 | * type |
| 36 | ******************************************************************************/ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 37 | #define INTR_RM_FLAGS_SHIFT U(0x0) |
| 38 | #define INTR_RM_FLAGS_MASK U(0x3) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 39 | /* Routed to EL3 from NS. Taken to S-EL1 from Secure */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 40 | #define INTR_SEL1_VALID_RM0 U(0x2) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 41 | /* Routed to EL3 from NS and Secure */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 42 | #define INTR_SEL1_VALID_RM1 U(0x3) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 43 | /* Routed to EL1/EL2 from NS and to S-EL1 from Secure */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 44 | #define INTR_NS_VALID_RM0 U(0x0) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 45 | /* Routed to EL1/EL2 from NS and to EL3 from Secure */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 46 | #define INTR_NS_VALID_RM1 U(0x1) |
Soby Mathew | 58e32d1 | 2015-11-23 13:58:45 +0000 | [diff] [blame] | 47 | /* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 48 | #define INTR_EL3_VALID_RM0 U(0x2) |
Soby Mathew | 58e32d1 | 2015-11-23 13:58:45 +0000 | [diff] [blame] | 49 | /* Routed to EL3 from NS and Secure */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 50 | #define INTR_EL3_VALID_RM1 U(0x3) |
Soby Mathew | 47903c0 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 51 | /* This is the default routing model */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 52 | #define INTR_DEFAULT_RM U(0x0) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 53 | |
| 54 | /******************************************************************************* |
| 55 | * Constants for the _individual_ routing model bits in the 'flags' field for |
| 56 | * each interrupt type and mask to validate the 'flags' parameter while |
| 57 | * registering an interrupt handler |
| 58 | ******************************************************************************/ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 59 | #define INTR_TYPE_FLAGS_MASK U(0xFFFFFFFC) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 60 | |
| 61 | #define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */ |
| 62 | #define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 63 | #define INTR_RM_FROM_FLAG_MASK U(1) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 64 | #define get_interrupt_rm_flag(flag, ss) (((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \ |
| 65 | & INTR_RM_FROM_FLAG_MASK) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 66 | #define set_interrupt_rm_flag(flag, ss) (flag |= U(1) << ss) |
| 67 | #define clr_interrupt_rm_flag(flag, ss) (flag &= ~(U(1) << ss)) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 68 | |
| 69 | |
| 70 | /******************************************************************************* |
| 71 | * Macros to validate the routing model bits in the 'flags' for a type |
| 72 | * of interrupt. If the model does not match one of the valid masks |
| 73 | * -EINVAL is returned. |
| 74 | ******************************************************************************/ |
Soby Mathew | 58e32d1 | 2015-11-23 13:58:45 +0000 | [diff] [blame] | 75 | #define validate_sel1_interrupt_rm(x) ((x) == INTR_SEL1_VALID_RM0 ? 0 : \ |
| 76 | ((x) == INTR_SEL1_VALID_RM1 ? 0 :\ |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 77 | -EINVAL)) |
| 78 | |
Soby Mathew | 58e32d1 | 2015-11-23 13:58:45 +0000 | [diff] [blame] | 79 | #define validate_ns_interrupt_rm(x) ((x) == INTR_NS_VALID_RM0 ? 0 : \ |
| 80 | ((x) == INTR_NS_VALID_RM1 ? 0 :\ |
| 81 | -EINVAL)) |
| 82 | |
Jeenu Viswambharan | f4194ee | 2018-01-10 15:00:20 +0000 | [diff] [blame] | 83 | #if EL3_EXCEPTION_HANDLING |
| 84 | /* |
| 85 | * With EL3 exception handling, EL3 interrupts are always routed to EL3 from |
| 86 | * both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is the only |
| 87 | * valid routing model. |
| 88 | */ |
| 89 | #define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM1 ? 0 : \ |
| 90 | -EINVAL) |
| 91 | #else |
Soby Mathew | 58e32d1 | 2015-11-23 13:58:45 +0000 | [diff] [blame] | 92 | #define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM0 ? 0 : \ |
| 93 | ((x) == INTR_EL3_VALID_RM1 ? 0 :\ |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 94 | -EINVAL)) |
Jeenu Viswambharan | f4194ee | 2018-01-10 15:00:20 +0000 | [diff] [blame] | 95 | #endif |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 96 | |
| 97 | /******************************************************************************* |
| 98 | * Macros to set the 'flags' parameter passed to an interrupt type handler. Only |
| 99 | * the flag to indicate the security state when the exception was generated is |
| 100 | * supported. |
| 101 | ******************************************************************************/ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 102 | #define INTR_SRC_SS_FLAG_SHIFT U(0) /* BIT[0] */ |
| 103 | #define INTR_SRC_SS_FLAG_MASK U(1) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 104 | #define set_interrupt_src_ss(flag, val) (flag |= val << INTR_SRC_SS_FLAG_SHIFT) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 105 | #define clr_interrupt_src_ss(flag) (flag &= ~(U(1) << INTR_SRC_SS_FLAG_SHIFT)) |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 106 | #define get_interrupt_src_ss(flag) ((flag >> INTR_SRC_SS_FLAG_SHIFT) & \ |
| 107 | INTR_SRC_SS_FLAG_MASK) |
| 108 | |
| 109 | #ifndef __ASSEMBLY__ |
| 110 | |
Jeenu Viswambharan | aeb267c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 111 | #include <stdint.h> |
| 112 | |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 113 | /* Prototype for defining a handler for an interrupt type */ |
| 114 | typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, |
| 115 | uint32_t flags, |
| 116 | void *handle, |
| 117 | void *cookie); |
| 118 | |
| 119 | /******************************************************************************* |
| 120 | * Function & variable prototypes |
| 121 | ******************************************************************************/ |
Dan Handley | a17fefa | 2014-05-14 12:38:32 +0100 | [diff] [blame] | 122 | uint32_t get_scr_el3_from_routing_model(uint32_t security_state); |
| 123 | int32_t set_routing_model(uint32_t type, uint32_t flags); |
| 124 | int32_t register_interrupt_type_handler(uint32_t type, |
| 125 | interrupt_type_handler_t handler, |
| 126 | uint32_t flags); |
Roberto Vargas | 777dd43 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 127 | interrupt_type_handler_t get_interrupt_type_handler(uint32_t type); |
Soby Mathew | 47903c0 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 128 | int disable_intr_rm_local(uint32_t type, uint32_t security_state); |
| 129 | int enable_intr_rm_local(uint32_t type, uint32_t security_state); |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 130 | |
| 131 | #endif /*__ASSEMBLY__*/ |
| 132 | #endif /* __INTERRUPT_MGMT_H__ */ |