Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 5 | */ |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 6 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <assert_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <common/debug.h> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 11 | #include <cortex_a53.h> |
| 12 | #include <cpu_macros.S> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 13 | |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 14 | #if A53_DISABLE_NON_TEMPORAL_HINT |
| 15 | #undef ERRATA_A53_836870 |
| 16 | #define ERRATA_A53_836870 1 |
| 17 | #endif |
| 18 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 19 | /* --------------------------------------------- |
| 20 | * Disable intra-cluster coherency |
| 21 | * --------------------------------------------- |
| 22 | */ |
| 23 | func cortex_a53_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 24 | ldcopr16 r0, r1, CORTEX_A53_ECTLR |
| 25 | bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT |
| 26 | stcopr16 r0, r1, CORTEX_A53_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 27 | isb |
| 28 | dsb sy |
| 29 | bx lr |
| 30 | endfunc cortex_a53_disable_smp |
| 31 | |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 32 | /* -------------------------------------------------- |
| 33 | * Errata Workaround for Cortex A53 Errata #826319. |
| 34 | * This applies only to revision <= r0p2 of Cortex A53. |
| 35 | * Inputs: |
| 36 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 37 | * Shall clobber: r0-r3 |
| 38 | * -------------------------------------------------- |
| 39 | */ |
| 40 | func errata_a53_826319_wa |
| 41 | /* |
| 42 | * Compare r0 against revision r0p2 |
| 43 | */ |
| 44 | mov r2, lr |
| 45 | bl check_errata_826319 |
| 46 | mov lr, r2 |
| 47 | cmp r0, #ERRATA_NOT_APPLIES |
| 48 | beq 1f |
| 49 | ldcopr r0, CORTEX_A53_L2ACTLR |
| 50 | bic r0, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN |
| 51 | orr r0, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH |
| 52 | stcopr r0, CORTEX_A53_L2ACTLR |
| 53 | 1: |
| 54 | bx lr |
| 55 | endfunc errata_a53_826319_wa |
| 56 | |
| 57 | func check_errata_826319 |
| 58 | mov r1, #0x02 |
| 59 | b cpu_rev_var_ls |
| 60 | endfunc check_errata_826319 |
| 61 | |
| 62 | /* --------------------------------------------------------------------- |
| 63 | * Disable the cache non-temporal hint. |
| 64 | * |
| 65 | * This ignores the Transient allocation hint in the MAIR and treats |
| 66 | * allocations the same as non-transient allocation types. As a result, |
| 67 | * the LDNP and STNP instructions in AArch64 behave the same as the |
| 68 | * equivalent LDP and STP instructions. |
| 69 | * |
| 70 | * This is relevant only for revisions <= r0p3 of Cortex-A53. |
| 71 | * From r0p4 and onwards, the bit to disable the hint is enabled by |
| 72 | * default at reset. |
| 73 | * |
| 74 | * Inputs: |
| 75 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 76 | * Shall clobber: r0-r3 |
| 77 | * --------------------------------------------------------------------- |
| 78 | */ |
| 79 | func a53_disable_non_temporal_hint |
| 80 | /* |
| 81 | * Compare r0 against revision r0p3 |
| 82 | */ |
| 83 | mov r2, lr |
| 84 | bl check_errata_disable_non_temporal_hint |
| 85 | mov lr, r2 |
| 86 | cmp r0, #ERRATA_NOT_APPLIES |
| 87 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 88 | ldcopr16 r0, r1, CORTEX_A53_CPUACTLR |
| 89 | orr64_imm r0, r1, CORTEX_A53_CPUACTLR_DTAH |
| 90 | stcopr16 r0, r1, CORTEX_A53_CPUACTLR |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 91 | 1: |
| 92 | bx lr |
| 93 | endfunc a53_disable_non_temporal_hint |
| 94 | |
| 95 | func check_errata_disable_non_temporal_hint |
| 96 | mov r1, #0x03 |
| 97 | b cpu_rev_var_ls |
| 98 | endfunc check_errata_disable_non_temporal_hint |
| 99 | |
| 100 | /* -------------------------------------------------- |
| 101 | * Errata Workaround for Cortex A53 Errata #855873. |
| 102 | * |
| 103 | * This applies only to revisions >= r0p3 of Cortex A53. |
| 104 | * Earlier revisions of the core are affected as well, but don't |
| 105 | * have the chicken bit in the CPUACTLR register. It is expected that |
| 106 | * the rich OS takes care of that, especially as the workaround is |
| 107 | * shared with other erratas in those revisions of the CPU. |
| 108 | * Inputs: |
| 109 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 110 | * Shall clobber: r0-r3 |
| 111 | * -------------------------------------------------- |
| 112 | */ |
| 113 | func errata_a53_855873_wa |
| 114 | /* |
| 115 | * Compare r0 against revision r0p3 and higher |
| 116 | */ |
| 117 | mov r2, lr |
| 118 | bl check_errata_855873 |
| 119 | mov lr, r2 |
| 120 | cmp r0, #ERRATA_NOT_APPLIES |
| 121 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 122 | ldcopr16 r0, r1, CORTEX_A53_CPUACTLR |
| 123 | orr64_imm r0, r1, CORTEX_A53_CPUACTLR_ENDCCASCI |
| 124 | stcopr16 r0, r1, CORTEX_A53_CPUACTLR |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 125 | 1: |
| 126 | bx lr |
| 127 | endfunc errata_a53_855873_wa |
| 128 | |
| 129 | func check_errata_855873 |
| 130 | mov r1, #0x03 |
| 131 | b cpu_rev_var_hs |
| 132 | endfunc check_errata_855873 |
| 133 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 134 | /* ------------------------------------------------- |
| 135 | * The CPU Ops reset function for Cortex-A53. |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 136 | * Shall clobber: r0-r6 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 137 | * ------------------------------------------------- |
| 138 | */ |
| 139 | func cortex_a53_reset_func |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 140 | mov r5, lr |
| 141 | bl cpu_get_rev_var |
| 142 | mov r4, r0 |
| 143 | |
| 144 | #if ERRATA_A53_826319 |
| 145 | mov r0, r4 |
| 146 | bl errata_a53_826319_wa |
| 147 | #endif |
| 148 | |
| 149 | #if ERRATA_A53_836870 |
| 150 | mov r0, r4 |
| 151 | bl a53_disable_non_temporal_hint |
| 152 | #endif |
| 153 | |
| 154 | #if ERRATA_A53_855873 |
| 155 | mov r0, r4 |
| 156 | bl errata_a53_855873_wa |
| 157 | #endif |
| 158 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 159 | /* --------------------------------------------- |
| 160 | * Enable the SMP bit. |
| 161 | * --------------------------------------------- |
| 162 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 163 | ldcopr16 r0, r1, CORTEX_A53_ECTLR |
| 164 | orr64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT |
| 165 | stcopr16 r0, r1, CORTEX_A53_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 166 | isb |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 167 | bx r5 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 168 | endfunc cortex_a53_reset_func |
| 169 | |
| 170 | /* ---------------------------------------------------- |
| 171 | * The CPU Ops core power down function for Cortex-A53. |
| 172 | * ---------------------------------------------------- |
| 173 | */ |
| 174 | func cortex_a53_core_pwr_dwn |
| 175 | push {r12, lr} |
| 176 | |
| 177 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 178 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 179 | ldcopr r0, SCTLR |
| 180 | tst r0, #SCTLR_C_BIT |
| 181 | ASM_ASSERT(eq) |
| 182 | #endif |
| 183 | |
| 184 | /* --------------------------------------------- |
| 185 | * Flush L1 caches. |
| 186 | * --------------------------------------------- |
| 187 | */ |
| 188 | mov r0, #DC_OP_CISW |
| 189 | bl dcsw_op_level1 |
| 190 | |
| 191 | /* --------------------------------------------- |
| 192 | * Come out of intra cluster coherency |
| 193 | * --------------------------------------------- |
| 194 | */ |
| 195 | pop {r12, lr} |
| 196 | b cortex_a53_disable_smp |
| 197 | endfunc cortex_a53_core_pwr_dwn |
| 198 | |
| 199 | /* ------------------------------------------------------- |
| 200 | * The CPU Ops cluster power down function for Cortex-A53. |
| 201 | * Clobbers: r0-r3 |
| 202 | * ------------------------------------------------------- |
| 203 | */ |
| 204 | func cortex_a53_cluster_pwr_dwn |
| 205 | push {r12, lr} |
| 206 | |
| 207 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 208 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 209 | ldcopr r0, SCTLR |
| 210 | tst r0, #SCTLR_C_BIT |
| 211 | ASM_ASSERT(eq) |
| 212 | #endif |
| 213 | |
| 214 | /* --------------------------------------------- |
| 215 | * Flush L1 caches. |
| 216 | * --------------------------------------------- |
| 217 | */ |
| 218 | mov r0, #DC_OP_CISW |
| 219 | bl dcsw_op_level1 |
| 220 | |
| 221 | /* --------------------------------------------- |
| 222 | * Disable the optional ACP. |
| 223 | * --------------------------------------------- |
| 224 | */ |
| 225 | bl plat_disable_acp |
| 226 | |
| 227 | /* --------------------------------------------- |
| 228 | * Flush L2 caches. |
| 229 | * --------------------------------------------- |
| 230 | */ |
| 231 | mov r0, #DC_OP_CISW |
| 232 | bl dcsw_op_level2 |
| 233 | |
| 234 | /* --------------------------------------------- |
| 235 | * Come out of intra cluster coherency |
| 236 | * --------------------------------------------- |
| 237 | */ |
| 238 | pop {r12, lr} |
| 239 | b cortex_a53_disable_smp |
| 240 | endfunc cortex_a53_cluster_pwr_dwn |
| 241 | |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 242 | #if REPORT_ERRATA |
| 243 | /* |
| 244 | * Errata printing function for Cortex A53. Must follow AAPCS. |
| 245 | */ |
| 246 | func cortex_a53_errata_report |
| 247 | push {r12, lr} |
| 248 | |
| 249 | bl cpu_get_rev_var |
| 250 | mov r4, r0 |
| 251 | |
| 252 | /* |
| 253 | * Report all errata. The revision-variant information is passed to |
| 254 | * checking functions of each errata. |
| 255 | */ |
| 256 | report_errata ERRATA_A53_826319, cortex_a53, 826319 |
| 257 | report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint |
| 258 | report_errata ERRATA_A53_855873, cortex_a53, 855873 |
| 259 | |
| 260 | pop {r12, lr} |
| 261 | bx lr |
| 262 | endfunc cortex_a53_errata_report |
| 263 | #endif |
| 264 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 265 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ |
| 266 | cortex_a53_reset_func, \ |
| 267 | cortex_a53_core_pwr_dwn, \ |
| 268 | cortex_a53_cluster_pwr_dwn |