Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 1 | /* |
Mario Bălănică | cb759ff | 2023-12-06 21:36:25 +0200 | [diff] [blame] | 2 | * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. |
Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Andre Przywara | bb6ef15 | 2019-07-09 11:44:14 +0100 | [diff] [blame] | 7 | #ifndef RPI_HW_H |
| 8 | #define RPI_HW_H |
Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 11 | |
| 12 | /* |
| 13 | * Peripherals |
| 14 | */ |
| 15 | |
Andre Przywara | 4f4f769 | 2019-07-09 15:59:26 +0100 | [diff] [blame] | 16 | #define RPI_IO_BASE ULL(0x3F000000) |
| 17 | #define RPI_IO_SIZE ULL(0x01000000) |
Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 18 | |
| 19 | /* |
Antonio Nino Diaz | ecf3471 | 2018-07-12 13:38:53 +0100 | [diff] [blame] | 20 | * ARM <-> VideoCore mailboxes |
| 21 | */ |
| 22 | #define RPI3_MBOX_OFFSET ULL(0x0000B880) |
Andre Przywara | 4f4f769 | 2019-07-09 15:59:26 +0100 | [diff] [blame] | 23 | #define RPI3_MBOX_BASE (RPI_IO_BASE + RPI3_MBOX_OFFSET) |
Antonio Nino Diaz | ecf3471 | 2018-07-12 13:38:53 +0100 | [diff] [blame] | 24 | |
| 25 | /* |
Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 26 | * Power management, reset controller, watchdog. |
| 27 | */ |
| 28 | #define RPI3_IO_PM_OFFSET ULL(0x00100000) |
Andre Przywara | 4f4f769 | 2019-07-09 15:59:26 +0100 | [diff] [blame] | 29 | #define RPI3_PM_BASE (RPI_IO_BASE + RPI3_IO_PM_OFFSET) |
Antonio Nino Diaz | 6942f05 | 2018-07-14 02:15:51 +0100 | [diff] [blame] | 30 | |
| 31 | /* |
Antonio Nino Diaz | 12f73ff | 2018-07-13 09:27:16 +0100 | [diff] [blame] | 32 | * Hardware random number generator. |
| 33 | */ |
| 34 | #define RPI3_IO_RNG_OFFSET ULL(0x00104000) |
Andre Przywara | 4f4f769 | 2019-07-09 15:59:26 +0100 | [diff] [blame] | 35 | #define RPI3_RNG_BASE (RPI_IO_BASE + RPI3_IO_RNG_OFFSET) |
Antonio Nino Diaz | 12f73ff | 2018-07-13 09:27:16 +0100 | [diff] [blame] | 36 | |
| 37 | /* |
Andre Przywara | 9ba6bb0 | 2020-03-10 12:34:56 +0000 | [diff] [blame] | 38 | * Serial ports: |
| 39 | * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART. |
| 40 | * There is also a PL011 UART, multiplexed to the same pins. |
Antonio Nino Diaz | 6942f05 | 2018-07-14 02:15:51 +0100 | [diff] [blame] | 41 | */ |
| 42 | #define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) |
Andre Przywara | 4f4f769 | 2019-07-09 15:59:26 +0100 | [diff] [blame] | 43 | #define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET) |
Andre Przywara | 9ba6bb0 | 2020-03-10 12:34:56 +0000 | [diff] [blame] | 44 | #define RPI3_IO_PL011_UART_OFFSET ULL(0x00201000) |
| 45 | #define RPI3_PL011_UART_BASE (RPI_IO_BASE + RPI3_IO_PL011_UART_OFFSET) |
| 46 | #define RPI3_PL011_UART_CLOCK ULL(48000000) |
Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 47 | |
| 48 | /* |
Ying-Chun Liu (PaulLiu) | 3452738 | 2019-01-22 03:27:55 +0800 | [diff] [blame] | 49 | * GPIO controller |
| 50 | */ |
| 51 | #define RPI3_IO_GPIO_OFFSET ULL(0x00200000) |
Andre Przywara | 4f4f769 | 2019-07-09 15:59:26 +0100 | [diff] [blame] | 52 | #define RPI3_GPIO_BASE (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET) |
Ying-Chun Liu (PaulLiu) | 3452738 | 2019-01-22 03:27:55 +0800 | [diff] [blame] | 53 | |
| 54 | /* |
Ying-Chun Liu (PaulLiu) | de6f2f4 | 2019-01-30 04:20:38 +0800 | [diff] [blame] | 55 | * SDHost controller |
| 56 | */ |
| 57 | #define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) |
Andre Przywara | 4f4f769 | 2019-07-09 15:59:26 +0100 | [diff] [blame] | 58 | #define RPI3_SDHOST_BASE (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET) |
Ying-Chun Liu (PaulLiu) | de6f2f4 | 2019-01-30 04:20:38 +0800 | [diff] [blame] | 59 | |
| 60 | /* |
Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 61 | * Local interrupt controller |
| 62 | */ |
| 63 | #define RPI3_INTC_BASE_ADDRESS ULL(0x40000000) |
| 64 | /* Registers on top of RPI3_INTC_BASE_ADDRESS */ |
| 65 | #define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000) |
| 66 | #define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008) |
| 67 | #define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050) |
| 68 | #define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080) |
| 69 | #define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070) |
| 70 | #define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080) |
| 71 | |
Andre Przywara | bb6ef15 | 2019-07-09 11:44:14 +0100 | [diff] [blame] | 72 | #endif /* RPI_HW_H */ |