blob: 12e7db43a67832ccde24245b3d5c32f2b96c7fe7 [file] [log] [blame]
Rohit Mathew1d1c1422024-02-12 18:54:15 +00001# Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
Aditya Angadid61740b2020-11-19 18:05:33 +05302#
3# SPDX-License-Identifier: BSD-3-Clause
4#
5
Tony K Nadackala81a3d92021-11-24 16:09:26 +00006RD_N2_VARIANTS := 0 1 2 3
Rohit Mathew644d9e22024-02-03 19:06:16 +00007ifneq ($(NRD_PLATFORM_VARIANT),\
8 $(filter $(NRD_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
9 $(error "NRD_PLATFORM_VARIANT for RD-N2 should be 0, 1, 2 or 3, currently \
10 set to ${NRD_PLATFORM_VARIANT}.")
Aditya Angadiccae8a12021-08-09 09:38:58 +053011endif
12
13$(eval $(call CREATE_SEQ,SEQ,4))
Rohit Mathew644d9e22024-02-03 19:06:16 +000014ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
Aditya Angadiccae8a12021-08-09 09:38:58 +053015 $(error "Chip count for RD-N2-MC should be either $(SEQ) \
Rohit Mathew644d9e22024-02-03 19:06:16 +000016 currently it is set to ${NRD_CHIP_COUNT}.")
Aditya Angadiccae8a12021-08-09 09:38:58 +053017endif
18
Andre Przywarab6c24ce2021-07-20 19:20:07 +010019# RD-N2 platform uses GIC-700 which is based on GICv4.1
Aditya Angadid61740b2020-11-19 18:05:33 +053020GIC_ENABLE_V4_EXTN := 1
Vivek Gautam44a91512022-09-14 13:44:52 +053021GIC_EXT_INTID := 1
Aditya Angadid61740b2020-11-19 18:05:33 +053022
Aditya Angadiccae8a12021-08-09 09:38:58 +053023#Enable GIC Multichip Extension only for Multichip Platforms
Rohit Mathew644d9e22024-02-03 19:06:16 +000024ifeq (${NRD_PLATFORM_VARIANT}, 2)
Aditya Angadiccae8a12021-08-09 09:38:58 +053025GICV3_IMPL_GIC600_MULTICHIP := 1
26endif
27
Pranav Madhu078dc522022-07-27 14:01:24 +053028override CSS_SYSTEM_GRACEFUL_RESET := 1
29override EL3_EXCEPTION_HANDLING := 1
30
Rohit Mathew20d4a212024-02-03 21:20:17 +000031include plat/arm/board/neoverse_rd/common/nrd-common.mk
Aditya Angadid61740b2020-11-19 18:05:33 +053032
Rohit Mathew20d4a212024-02-03 21:20:17 +000033RDN2_BASE = plat/arm/board/neoverse_rd/platform/rdn2
Aditya Angadid61740b2020-11-19 18:05:33 +053034
35PLAT_INCLUDES += -I${RDN2_BASE}/include/
36
Rohit Mathew6521c1d2024-02-03 22:23:25 +000037NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \
Joel Goddarda1c50ab2022-09-21 21:52:28 +053038 lib/cpus/aarch64/neoverse_v2.S
Aditya Angadid61740b2020-11-19 18:05:33 +053039
Rohit Mathew20d4a212024-02-03 21:20:17 +000040PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat_v2.c
Aditya Angadid61740b2020-11-19 18:05:33 +053041
Rohit Mathew6521c1d2024-02-03 22:23:25 +000042BL1_SOURCES += ${NRD_CPU_SOURCES} \
Aditya Angadid61740b2020-11-19 18:05:33 +053043 ${RDN2_BASE}/rdn2_err.c
44
45BL2_SOURCES += ${RDN2_BASE}/rdn2_plat.c \
46 ${RDN2_BASE}/rdn2_security.c \
47 ${RDN2_BASE}/rdn2_err.c \
48 lib/utils/mem_region.c \
49 drivers/arm/tzc/tzc400.c \
50 plat/arm/common/arm_tzc400.c \
51 plat/arm/common/arm_nor_psci_mem_protect.c
52
Rohit Mathew6521c1d2024-02-03 22:23:25 +000053BL31_SOURCES += ${NRD_CPU_SOURCES} \
Aditya Angadid61740b2020-11-19 18:05:33 +053054 ${RDN2_BASE}/rdn2_plat.c \
55 ${RDN2_BASE}/rdn2_topology.c \
56 drivers/cfi/v2m/v2m_flash.c \
57 lib/utils/mem_region.c \
58 plat/arm/common/arm_nor_psci_mem_protect.c
59
60ifeq (${TRUSTED_BOARD_BOOT}, 1)
61BL1_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
62BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
63endif
64
Rohit Mathew644d9e22024-02-03 19:06:16 +000065ifeq (${NRD_PLATFORM_VARIANT}, 2)
Aditya Angadiccae8a12021-08-09 09:38:58 +053066BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
67
68# Enable dynamic addition of MMAP regions in BL31
69BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
70endif
71
Manish Pandeyf90a73c2023-10-10 15:42:19 +010072ifeq (${ENABLE_FEAT_RAS}-${HANDLE_EA_EL3_FIRST_NS},1-1)
Omkar Anand Kulkarni1f425992023-06-22 15:18:07 +053073BL31_SOURCES += ${RDN2_BASE}/rdn2_ras.c \
Rohit Mathew20d4a212024-02-03 21:20:17 +000074 ${NRD_COMMON_BASE}/ras/nrd_ras_common.c \
75 ${NRD_COMMON_BASE}/ras/nrd_ras_sram.c \
76 ${NRD_COMMON_BASE}/ras/nrd_ras_cpu.c
Omkar Anand Kulkarni1f425992023-06-22 15:18:07 +053077endif
78
Aditya Angadid61740b2020-11-19 18:05:33 +053079# Add the FDT_SOURCES and options for Dynamic Config
80FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \
81 ${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts
82FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
83TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
84
85# Add the FW_CONFIG to FIP and specify the same to certtool
86$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
87# Add the TB_FW_CONFIG to FIP and specify the same to certtool
88$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
89
90FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_nt_fw_config.dts
91NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
92
93# Add the NT_FW_CONFIG to FIP and specify the same to certtool
94$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
95
Rohit Mathew1d1c1422024-02-12 18:54:15 +000096ifeq (${SPMC_AT_EL3}, 1)
Sayanta Pattanayak2a10dc82021-11-17 20:08:19 +053097STMM_CONFIG_DTS := ${RDN2_BASE}/fdts/${PLAT}_stmm_sel0_manifest.dts
98FDT_SOURCES += ${STMM_CONFIG_DTS}
99TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${STMM_CONFIG_DTS})).dtb
100
101# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
102$(eval $(call TOOL_ADD_PAYLOAD,${TOS_FW_CONFIG},--tos-fw-config,${TOS_FW_CONFIG}))
Rohit Mathew1d1c1422024-02-12 18:54:15 +0000103endif
Sayanta Pattanayak2a10dc82021-11-17 20:08:19 +0530104
Aditya Angadid61740b2020-11-19 18:05:33 +0530105override CTX_INCLUDE_AARCH32_REGS := 0
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000106override ENABLE_FEAT_AMU := 1
Nuno Lopes8f3bd472023-11-28 12:19:24 +0000107
108# Enable the flag since RD-N2 has a system level cache
109NEOVERSE_Nx_EXTERNAL_LLC := 1
Thomas Abraham9f22f3f2023-12-10 17:27:36 +0000110
111# Enable N2 CPU errata workarounds
112ERRATA_N2_2002655 := 1
113ERRATA_N2_2009478 := 1
114ERRATA_N2_2067956 := 1
115ERRATA_N2_2025414 := 1
116ERRATA_N2_2189731 := 1
117ERRATA_N2_2138956 := 1
118ERRATA_N2_2138953 := 1
119ERRATA_N2_2242415 := 1
120ERRATA_N2_2138958 := 1
121ERRATA_N2_2242400 := 1
122ERRATA_N2_2280757 := 1
123ERRATA_N2_2326639 := 1
124ERRATA_N2_2340933 := 1
125ERRATA_N2_2346952 := 1
126ERRATA_N2_2376738 := 1
127ERRATA_N2_2388450 := 1
128ERRATA_N2_2743014 := 1
129ERRATA_N2_2743089 := 1
130ERRATA_N2_2728475 := 1
131ERRATA_N2_2779511 := 1