Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <assert.h> |
| 32 | #include <bl_common.h> |
| 33 | #include <arch.h> |
| 34 | #include <arch_helpers.h> |
| 35 | #include <context.h> |
| 36 | #include <context_mgmt.h> |
| 37 | #include <cpu_data.h> |
| 38 | #include <debug.h> |
| 39 | #include <platform.h> |
| 40 | #include <runtime_svc.h> |
| 41 | #include <stddef.h> |
| 42 | #include "psci_private.h" |
| 43 | |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 44 | /******************************************************************************* |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 45 | * This function does generic and platform specific operations after a wake-up |
| 46 | * from standby/retention states at multiple power levels. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 47 | ******************************************************************************/ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 48 | static void psci_suspend_to_standby_finisher(unsigned int cpu_idx, |
| 49 | psci_power_state_t *state_info, |
| 50 | unsigned int end_pwrlvl) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 51 | { |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 52 | psci_acquire_pwr_domain_locks(end_pwrlvl, |
| 53 | cpu_idx); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 54 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 55 | /* |
| 56 | * Plat. management: Allow the platform to do operations |
| 57 | * on waking up from retention. |
| 58 | */ |
| 59 | psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 60 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 61 | /* |
| 62 | * Set the requested and target state of this CPU and all the higher |
| 63 | * power domain levels for this CPU to run. |
| 64 | */ |
| 65 | psci_set_pwr_domains_to_run(end_pwrlvl); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 66 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 67 | psci_release_pwr_domain_locks(end_pwrlvl, |
| 68 | cpu_idx); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 69 | } |
| 70 | |
| 71 | /******************************************************************************* |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 72 | * This function does generic and platform specific suspend to power down |
| 73 | * operations. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 74 | ******************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 75 | static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl, |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 76 | entry_point_info_t *ep, |
| 77 | psci_power_state_t *state_info) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 78 | { |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 79 | /* Save PSCI target power level for the suspend finisher handler */ |
| 80 | psci_set_suspend_pwrlvl(end_pwrlvl); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 81 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 82 | /* |
| 83 | * Flush the target power level as it will be accessed on power up with |
| 84 | * Data cache disabled. |
| 85 | */ |
| 86 | flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 87 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 88 | /* |
| 89 | * Call the cpu suspend handler registered by the Secure Payload |
| 90 | * Dispatcher to let it do any book-keeping. If the handler encounters an |
| 91 | * error, it's expected to assert within |
| 92 | */ |
| 93 | if (psci_spd_pm && psci_spd_pm->svc_suspend) |
| 94 | psci_spd_pm->svc_suspend(0); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 95 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 96 | /* |
| 97 | * Store the re-entry information for the non-secure world. |
| 98 | */ |
| 99 | cm_init_my_context(ep); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 100 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 101 | /* |
| 102 | * Arch. management. Perform the necessary steps to flush all |
| 103 | * cpu caches. Currently we assume that the power level correspond |
| 104 | * the cache level. |
| 105 | * TODO : Introduce a mechanism to query the cache level to flush |
| 106 | * and the cpu-ops power down to perform from the platform. |
| 107 | */ |
| 108 | psci_do_pwrdown_cache_maintenance(psci_find_max_off_lvl(state_info)); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | /******************************************************************************* |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 112 | * Top level handler which is called when a cpu wants to suspend its execution. |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 113 | * It is assumed that along with suspending the cpu power domain, power domains |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 114 | * at higher levels until the target power level will be suspended as well. It |
| 115 | * coordinates with the platform to negotiate the target state for each of |
| 116 | * the power domain level till the target power domain level. It then performs |
| 117 | * generic, architectural, platform setup and state management required to |
| 118 | * suspend that power domain level and power domain levels below it. |
| 119 | * e.g. For a cpu that's to be suspended, it could mean programming the |
| 120 | * power controller whereas for a cluster that's to be suspended, it will call |
| 121 | * the platform specific code which will disable coherency at the interconnect |
| 122 | * level if the cpu is the last in the cluster and also the program the power |
| 123 | * controller. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 124 | * |
| 125 | * All the required parameter checks are performed at the beginning and after |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame] | 126 | * the state transition has been done, no further error is expected and it is |
| 127 | * not possible to undo any of the actions taken beyond that point. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 128 | ******************************************************************************/ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 129 | void psci_cpu_suspend_start(entry_point_info_t *ep, |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 130 | unsigned int end_pwrlvl, |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 131 | psci_power_state_t *state_info, |
| 132 | unsigned int is_power_down_state) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 133 | { |
| 134 | int skip_wfi = 0; |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 135 | unsigned int idx = plat_my_core_pos(); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 136 | |
| 137 | /* |
| 138 | * This function must only be called on platforms where the |
| 139 | * CPU_SUSPEND platform hooks have been implemented. |
| 140 | */ |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 141 | assert(psci_plat_pm_ops->pwr_domain_suspend && |
| 142 | psci_plat_pm_ops->pwr_domain_suspend_finish); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 143 | |
| 144 | /* |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 145 | * This function acquires the lock corresponding to each power |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 146 | * level so that by the time all locks are taken, the system topology |
| 147 | * is snapshot and state management can be done safely. |
| 148 | */ |
Soby Mathew | 9d754f6 | 2015-04-08 17:42:06 +0100 | [diff] [blame] | 149 | psci_acquire_pwr_domain_locks(end_pwrlvl, |
| 150 | idx); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 151 | |
| 152 | /* |
| 153 | * We check if there are any pending interrupts after the delay |
| 154 | * introduced by lock contention to increase the chances of early |
| 155 | * detection that a wake-up interrupt has fired. |
| 156 | */ |
| 157 | if (read_isr_el1()) { |
| 158 | skip_wfi = 1; |
| 159 | goto exit; |
| 160 | } |
| 161 | |
| 162 | /* |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 163 | * This function is passed the requested state info and |
| 164 | * it returns the negotiated state info for each power level upto |
| 165 | * the end level specified. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 166 | */ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 167 | psci_do_state_coordination(end_pwrlvl, state_info); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 168 | |
Sandrine Bailleux | 574d685 | 2015-06-11 10:46:48 +0100 | [diff] [blame] | 169 | if (is_power_down_state) |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 170 | psci_suspend_to_pwrdown_start(end_pwrlvl, ep, state_info); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 171 | |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame] | 172 | /* |
| 173 | * Plat. management: Allow the platform to perform the |
| 174 | * necessary actions to turn off this cpu e.g. set the |
| 175 | * platform defined mailbox with the psci entrypoint, |
| 176 | * program the power controller etc. |
| 177 | */ |
Sandrine Bailleux | 574d685 | 2015-06-11 10:46:48 +0100 | [diff] [blame] | 178 | psci_plat_pm_ops->pwr_domain_suspend(state_info); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 179 | |
| 180 | exit: |
| 181 | /* |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 182 | * Release the locks corresponding to each power level in the |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 183 | * reverse order to which they were acquired. |
| 184 | */ |
Soby Mathew | 9d754f6 | 2015-04-08 17:42:06 +0100 | [diff] [blame] | 185 | psci_release_pwr_domain_locks(end_pwrlvl, |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 186 | idx); |
| 187 | if (skip_wfi) |
| 188 | return; |
| 189 | |
| 190 | if (is_power_down_state) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 191 | psci_power_down_wfi(); |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 192 | |
| 193 | /* |
| 194 | * We will reach here if only retention/standby states have been |
| 195 | * requested at multiple power levels. This means that the cpu |
| 196 | * context will be preserved. |
| 197 | */ |
| 198 | wfi(); |
| 199 | |
| 200 | /* |
| 201 | * After we wake up from context retaining suspend, call the |
| 202 | * context retaining suspend finisher. |
| 203 | */ |
| 204 | psci_suspend_to_standby_finisher(idx, state_info, end_pwrlvl); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 205 | } |
| 206 | |
| 207 | /******************************************************************************* |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 208 | * The following functions finish an earlier suspend request. They |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 209 | * are called by the common finisher routine in psci_common.c. The `state_info` |
| 210 | * is the psci_power_state from which this CPU has woken up from. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 211 | ******************************************************************************/ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 212 | void psci_cpu_suspend_finish(unsigned int cpu_idx, |
| 213 | psci_power_state_t *state_info) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 214 | { |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 215 | unsigned long long counter_freq; |
| 216 | unsigned int suspend_level; |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 217 | |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 218 | /* Ensure we have been woken up from a suspended state */ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 219 | assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\ |
| 220 | state_info->pwr_domain_state[PSCI_CPU_PWR_LVL])); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 221 | |
| 222 | /* |
| 223 | * Plat. management: Perform the platform specific actions |
| 224 | * before we change the state of the cpu e.g. enabling the |
| 225 | * gic or zeroing the mailbox register. If anything goes |
| 226 | * wrong then assert as there is no way to recover from this |
| 227 | * situation. |
| 228 | */ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 229 | psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 230 | |
| 231 | /* |
| 232 | * Arch. management: Enable the data cache, manage stack memory and |
| 233 | * restore the stashed EL3 architectural context from the 'cpu_context' |
| 234 | * structure for this cpu. |
| 235 | */ |
| 236 | psci_do_pwrup_cache_maintenance(); |
| 237 | |
| 238 | /* Re-init the cntfrq_el0 register */ |
| 239 | counter_freq = plat_get_syscnt_freq(); |
| 240 | write_cntfrq_el0(counter_freq); |
| 241 | |
| 242 | /* |
| 243 | * Call the cpu suspend finish handler registered by the Secure Payload |
| 244 | * Dispatcher to let it do any bookeeping. If the handler encounters an |
| 245 | * error, it's expected to assert within |
| 246 | */ |
| 247 | if (psci_spd_pm && psci_spd_pm->svc_suspend) { |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 248 | suspend_level = psci_get_suspend_pwrlvl(); |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 249 | assert (suspend_level != PSCI_INVALID_PWR_LVL); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 250 | psci_spd_pm->svc_suspend_finish(suspend_level); |
| 251 | } |
| 252 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 253 | /* Invalidate the suspend level for the cpu */ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 254 | psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 255 | |
| 256 | /* |
| 257 | * Generic management: Now we just need to retrieve the |
| 258 | * information that we had stashed away during the suspend |
| 259 | * call to set this cpu on its way. |
| 260 | */ |
| 261 | cm_prepare_el3_exit(NON_SECURE); |
| 262 | |
| 263 | /* Clean caches before re-entering normal world */ |
| 264 | dcsw_op_louis(DCCSW); |
| 265 | } |