| Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 1 | /* |
| Jimmy Brisson | 7ec175e | 2020-06-01 16:49:34 -0500 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, ARM Limited. All rights reserved. |
| Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 7 | #ifndef CORTEX_A78_H |
| 8 | #define CORTEX_A78_H |
| Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 12 | #define CORTEX_A78_MIDR U(0x410FD410) |
| Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 13 | |
| 14 | /******************************************************************************* |
| 15 | * CPU Extended Control register specific definitions. |
| 16 | ******************************************************************************/ |
| Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 17 | #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 |
| Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 18 | |
| 19 | /******************************************************************************* |
| 20 | * CPU Power Control register specific definitions |
| 21 | ******************************************************************************/ |
| Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 22 | #define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 23 | #define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) |
| Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 24 | |
| Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 25 | /******************************************************************************* |
| 26 | * CPU Auxiliary Control register specific definitions. |
| 27 | ******************************************************************************/ |
| Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 28 | #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) |
| Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 29 | |
| Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 30 | #define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1 |
| 31 | #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) |
| Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 32 | |
| Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 33 | /******************************************************************************* |
| 34 | * CPU Activity Monitor Unit register specific definitions. |
| 35 | ******************************************************************************/ |
| 36 | #define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 |
| 37 | #define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 |
| 38 | #define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 |
| 39 | #define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 |
| 40 | |
| Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 41 | #define CORTEX_A78_AMU_GROUP0_MASK U(0xF) |
| 42 | #define CORTEX_A78_AMU_GROUP1_MASK U(0x7) |
| Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 43 | |
| Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 44 | #endif /* CORTEX_A78_H */ |