blob: 34e50ea13367ce102e83a69269d76c4dd1ab3970 [file] [log] [blame]
Oliver Swede8fed2fe2019-11-11 11:11:06 +00001#
2# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Andre Przywaraeec45eb2020-01-24 15:02:27 +00007include lib/libfdt/libfdt.mk
8
Oliver Swede8fed2fe2019-11-11 11:11:06 +00009RESET_TO_BL31 := 1
10ifeq (${RESET_TO_BL31}, 0)
11$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
12endif
13
Oliver Swede3769b3f2019-12-16 14:08:27 +000014ifeq (${ENABLE_PIE}, 1)
15override SEPARATE_CODE_AND_RODATA := 1
16endif
17
Oliver Swede8fed2fe2019-11-11 11:11:06 +000018CTX_INCLUDE_AARCH32_REGS := 0
19ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
20$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
21endif
22
23ifeq (${TRUSTED_BOARD_BOOT}, 1)
24$(error "TRUSTED_BOARD_BOOT must be disabled")
25endif
26
27ifndef PRELOADED_BL33_BASE
28$(error "PRELOADED_BL33_BASE is not set")
29endif
30
31ifndef FPGA_PRELOADED_DTB_BASE
32$(error "FPGA_PRELOADED_DTB_BASE is not set")
33else
34$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
35endif
36
37# Treating this as a memory-constrained port for now
38USE_COHERENT_MEM := 0
39
Oliver Swede7fbb9b52020-01-15 10:20:09 +000040# This can be overridden depending on CPU(s) used in the FPGA image
Oliver Swede8fed2fe2019-11-11 11:11:06 +000041HW_ASSISTED_COHERENCY := 1
42
Andre Przywara8b505252020-04-09 10:10:09 +010043PL011_GENERIC_UART := 1
44
Oliver Swede7fbb9b52020-01-15 10:20:09 +000045FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
46
47# select a different set of CPU files, depending on whether we compile for
48# hardware assisted coherency cores or not
49ifeq (${HW_ASSISTED_COHERENCY}, 0)
50# Cores used without DSU
51 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
52 lib/cpus/aarch64/cortex_a53.S \
53 lib/cpus/aarch64/cortex_a57.S \
54 lib/cpus/aarch64/cortex_a72.S \
55 lib/cpus/aarch64/cortex_a73.S
56else
57# AArch64-only cores
58 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
59 lib/cpus/aarch64/cortex_a76ae.S \
60 lib/cpus/aarch64/cortex_a77.S \
Jimmy Brisson7ec175e2020-06-01 16:49:34 -050061 lib/cpus/aarch64/cortex_a78.S \
Oliver Swede7fbb9b52020-01-15 10:20:09 +000062 lib/cpus/aarch64/neoverse_n1.S \
63 lib/cpus/aarch64/neoverse_e1.S \
64 lib/cpus/aarch64/neoverse_zeus.S \
Oliver Swede7fbb9b52020-01-15 10:20:09 +000065 lib/cpus/aarch64/cortex_hercules_ae.S \
66 lib/cpus/aarch64/cortex_a65.S \
67 lib/cpus/aarch64/cortex_a65ae.S
68# AArch64/AArch32 cores
69 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
70 lib/cpus/aarch64/cortex_a75.S
71endif
Oliver Swede8fed2fe2019-11-11 11:11:06 +000072
Andre Przywarae1cc1302020-03-25 15:50:38 +000073# Allow detection of GIC-600
74GICV3_SUPPORT_GIC600 := 1
Manish Pandeyb21cad72020-04-03 18:59:20 +010075
76# Include GICv3 driver files
77include drivers/arm/gic/v3/gicv3.mk
78
79FPGA_GIC_SOURCES := ${GICV3_SOURCES} \
Oliver Swedeb51da812019-12-03 14:08:21 +000080 plat/common/plat_gicv3.c \
81 plat/arm/board/arm_fpga/fpga_gicv3.c
Oliver Swede8fed2fe2019-11-11 11:11:06 +000082
83PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
84
85PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
86
Andre Przywaraeec45eb2020-01-24 15:02:27 +000087BL31_SOURCES += common/fdt_wrappers.c \
88 drivers/delay_timer/delay_timer.c \
Oliver Swede8fed2fe2019-11-11 11:11:06 +000089 drivers/delay_timer/generic_delay_timer.c \
90 drivers/arm/pl011/${ARCH}/pl011_console.S \
91 plat/common/plat_psci_common.c \
92 plat/arm/board/arm_fpga/fpga_pm.c \
93 plat/arm/board/arm_fpga/fpga_topology.c \
94 plat/arm/board/arm_fpga/fpga_console.c \
95 plat/arm/board/arm_fpga/fpga_bl31_setup.c \
96 ${FPGA_CPU_LIBS} \
97 ${FPGA_GIC_SOURCES}
98
99all: bl31