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Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Antonio Nino Diaze40306b2017-01-13 15:03:07 +00002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
7#ifndef __ARCH_HELPERS_H__
8#define __ARCH_HELPERS_H__
9
10#include <arch.h> /* for additional register definitions */
11#include <stdint.h>
Antonio Nino Diaze40306b2017-01-13 15:03:07 +000012#include <sys/types.h>
Soby Mathewc6820d12016-05-09 17:49:55 +010013
14/**********************************************************************
15 * Macros which create inline functions to read or write CPU system
16 * registers
17 *********************************************************************/
18
19#define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
20static inline void write_## _name(u_register_t v) \
21{ \
22 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
23}
24
25#define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
26static inline u_register_t read_ ## _name(void) \
27{ \
28 u_register_t v; \
29 __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\
30 return v; \
31}
32
33/*
34 * The undocumented %Q and %R extended asm are used to implemented the below
35 * 64 bit `mrrc` and `mcrr` instructions. It works only on Little Endian
36 * systems for GCC versions < 4.6. Above GCC 4.6, both Little Endian and
37 * Big Endian systems generate the right instruction encoding.
38 */
dp-arm320e8442017-05-02 12:00:08 +010039#if !(__clang__ || __GNUC__ > (4) || __GNUC__ == (4) && __GNUC_MINOR__ >= (6))
40#error "clang or GCC 4.6 or above is required to build AArch32 Trusted Firmware"
Soby Mathewc6820d12016-05-09 17:49:55 +010041#endif
42
43#define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \
44static inline void write64_## _name(uint64_t v) \
45{ \
46 __asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\
47}
48
49#define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \
50static inline uint64_t read64_## _name(void) \
51{ uint64_t v; \
52 __asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\
53 return v; \
54}
55
56#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
57static inline u_register_t read_ ## _name(void) \
58{ \
59 u_register_t v; \
60 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
61 return v; \
62}
63
64#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
65static inline void write_ ## _name(u_register_t v) \
66{ \
67 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
68}
69
70#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \
71static inline void write_ ## _name(const u_register_t v) \
72{ \
73 __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \
74}
75
76/* Define read function for coproc register */
77#define DEFINE_COPROCR_READ_FUNC(_name, ...) \
78 _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__)
79
80/* Define read & write function for coproc register */
81#define DEFINE_COPROCR_RW_FUNCS(_name, ...) \
82 _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) \
83 _DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__)
84
85/* Define 64 bit read function for coproc register */
86#define DEFINE_COPROCR_READ_FUNC_64(_name, ...) \
87 _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__)
88
89/* Define 64 bit read & write function for coproc register */
90#define DEFINE_COPROCR_RW_FUNCS_64(_name, ...) \
91 _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) \
92 _DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__)
93
94/* Define read & write function for system register */
95#define DEFINE_SYSREG_RW_FUNCS(_name) \
96 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
97 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
98
99/**********************************************************************
100 * Macros to create inline functions for tlbi operations
101 *********************************************************************/
102
Dimitris Papastamos12f8be52017-06-20 09:25:10 +0100103#if ERRATA_A57_813419
104/*
105 * Define function for TLBI instruction with type specifier that
106 * implements the workaround for errata 813419 of Cortex-A57
107 */
Soby Mathewc6820d12016-05-09 17:49:55 +0100108#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
109static inline void tlbi##_op(void) \
110{ \
111 u_register_t v = 0; \
112 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
Dimitris Papastamos12f8be52017-06-20 09:25:10 +0100113 __asm__ volatile ("dsb ish");\
114 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
Soby Mathewc6820d12016-05-09 17:49:55 +0100115}
116
Dimitris Papastamos12f8be52017-06-20 09:25:10 +0100117#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
118static inline void tlbi##_op(u_register_t v) \
119{ \
120 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
121 __asm__ volatile ("dsb ish");\
122 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
123}
124#else
125#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
126static inline void tlbi##_op(void) \
Antonio Nino Diazac998032017-02-27 17:23:54 +0000127{ \
128 u_register_t v = 0; \
129 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
130}
131
Soby Mathewc6820d12016-05-09 17:49:55 +0100132#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
133static inline void tlbi##_op(u_register_t v) \
134{ \
135 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
136}
Dimitris Papastamos12f8be52017-06-20 09:25:10 +0100137#endif /* ERRATA_A57_813419 */
138
139#define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
140static inline void bpi##_op(void) \
141{ \
142 u_register_t v = 0; \
143 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
144}
Soby Mathewc6820d12016-05-09 17:49:55 +0100145
146/* Define function for simple TLBI operation */
147#define DEFINE_TLBIOP_FUNC(_op, ...) \
148 _DEFINE_TLBIOP_FUNC(_op, __VA_ARGS__)
149
150/* Define function for TLBI operation with register parameter */
151#define DEFINE_TLBIOP_PARAM_FUNC(_op, ...) \
152 _DEFINE_TLBIOP_PARAM_FUNC(_op, __VA_ARGS__)
153
Antonio Nino Diazac998032017-02-27 17:23:54 +0000154/* Define function for simple BPI operation */
155#define DEFINE_BPIOP_FUNC(_op, ...) \
156 _DEFINE_BPIOP_FUNC(_op, __VA_ARGS__)
157
Soby Mathewc6820d12016-05-09 17:49:55 +0100158/**********************************************************************
159 * Macros to create inline functions for DC operations
160 *********************************************************************/
161#define _DEFINE_DCOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
162static inline void dc##_op(u_register_t v) \
163{ \
164 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
165}
166
167/* Define function for DC operation with register parameter */
168#define DEFINE_DCOP_PARAM_FUNC(_op, ...) \
169 _DEFINE_DCOP_PARAM_FUNC(_op, __VA_ARGS__)
170
171/**********************************************************************
172 * Macros to create inline functions for system instructions
173 *********************************************************************/
174 /* Define function for simple system instruction */
175#define DEFINE_SYSOP_FUNC(_op) \
176static inline void _op(void) \
177{ \
178 __asm__ (#_op); \
179}
180
181
182/* Define function for system instruction with type specifier */
183#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
184static inline void _op ## _type(void) \
185{ \
186 __asm__ (#_op " " #_type); \
187}
188
189/* Define function for system instruction with register parameter */
190#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
191static inline void _op ## _type(u_register_t v) \
192{ \
193 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
194}
195
196void flush_dcache_range(uintptr_t addr, size_t size);
197void clean_dcache_range(uintptr_t addr, size_t size);
198void inv_dcache_range(uintptr_t addr, size_t size);
199
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000200void dcsw_op_louis(u_register_t op_type);
201void dcsw_op_all(u_register_t op_type);
202
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100203void disable_mmu_secure(void);
204void disable_mmu_icache_secure(void);
205
Soby Mathewc6820d12016-05-09 17:49:55 +0100206DEFINE_SYSOP_FUNC(wfi)
207DEFINE_SYSOP_FUNC(wfe)
208DEFINE_SYSOP_FUNC(sev)
209DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
210DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000211DEFINE_SYSOP_TYPE_FUNC(dmb, st)
212DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Soby Mathewc6820d12016-05-09 17:49:55 +0100213DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000214DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Soby Mathewc6820d12016-05-09 17:49:55 +0100215DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100216DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
Soby Mathewc6820d12016-05-09 17:49:55 +0100217DEFINE_SYSOP_FUNC(isb)
218
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100219void __dead2 smc(uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3,
220 uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7);
221
Soby Mathewc6820d12016-05-09 17:49:55 +0100222DEFINE_SYSREG_RW_FUNCS(spsr)
223DEFINE_SYSREG_RW_FUNCS(cpsr)
224
225/*******************************************************************************
226 * System register accessor prototypes
227 ******************************************************************************/
228DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR)
229DEFINE_COPROCR_READ_FUNC(midr, MIDR)
230DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
231DEFINE_COPROCR_READ_FUNC(isr, ISR)
232DEFINE_COPROCR_READ_FUNC(clidr, CLIDR)
233DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64)
234
235DEFINE_COPROCR_RW_FUNCS(scr, SCR)
236DEFINE_COPROCR_RW_FUNCS(ctr, CTR)
237DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR)
Etienne Carriere70a004b2017-11-05 22:56:03 +0100238DEFINE_COPROCR_RW_FUNCS(actlr, ACTLR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100239DEFINE_COPROCR_RW_FUNCS(hsctlr, HSCTLR)
240DEFINE_COPROCR_RW_FUNCS(hcr, HCR)
241DEFINE_COPROCR_RW_FUNCS(hcptr, HCPTR)
242DEFINE_COPROCR_RW_FUNCS(cntfrq, CNTFRQ)
243DEFINE_COPROCR_RW_FUNCS(cnthctl, CNTHCTL)
244DEFINE_COPROCR_RW_FUNCS(mair0, MAIR0)
245DEFINE_COPROCR_RW_FUNCS(mair1, MAIR1)
246DEFINE_COPROCR_RW_FUNCS(ttbcr, TTBCR)
247DEFINE_COPROCR_RW_FUNCS(ttbr0, TTBR0)
248DEFINE_COPROCR_RW_FUNCS_64(ttbr0, TTBR0_64)
249DEFINE_COPROCR_RW_FUNCS(ttbr1, TTBR1)
250DEFINE_COPROCR_RW_FUNCS(vpidr, VPIDR)
251DEFINE_COPROCR_RW_FUNCS(vmpidr, VMPIDR)
252DEFINE_COPROCR_RW_FUNCS_64(vttbr, VTTBR_64)
253DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64)
254DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64)
255DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR)
David Cunadofee86532017-04-13 22:38:29 +0100256DEFINE_COPROCR_RW_FUNCS(hstr, HSTR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100257
258DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE)
259DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE)
260DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE)
261DEFINE_COPROCR_RW_FUNCS(icc_pmr_el1, ICC_PMR)
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100262DEFINE_COPROCR_RW_FUNCS(icc_rpr_el1, ICC_RPR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100263DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el3, ICC_MGRPEN1)
264DEFINE_COPROCR_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0)
265DEFINE_COPROCR_RW_FUNCS(icc_hppir0_el1, ICC_HPPIR0)
266DEFINE_COPROCR_RW_FUNCS(icc_hppir1_el1, ICC_HPPIR1)
267DEFINE_COPROCR_RW_FUNCS(icc_iar0_el1, ICC_IAR0)
268DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1)
269DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0)
270DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100271DEFINE_COPROCR_RW_FUNCS_64(icc_sgi0r_el1, ICC_SGI0R_EL1_64)
Soby Mathewc6820d12016-05-09 17:49:55 +0100272
David Cunado5f55e282016-10-31 17:37:34 +0000273DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
David Cunadoc14b08e2016-11-25 00:21:59 +0000274DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL)
David Cunado5f55e282016-10-31 17:37:34 +0000275DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
276
Etienne Carriere70a004b2017-11-05 22:56:03 +0100277DEFINE_COPROCR_RW_FUNCS(nsacr, NSACR)
278
279/* AArch32 coproc registers for 32bit MMU descriptor support */
280DEFINE_COPROCR_RW_FUNCS(prrr, PRRR)
281DEFINE_COPROCR_RW_FUNCS(nmrr, NMRR)
282DEFINE_COPROCR_RW_FUNCS(dacr, DACR)
283
Soby Mathewc6820d12016-05-09 17:49:55 +0100284/*
285 * TLBI operation prototypes
286 */
287DEFINE_TLBIOP_FUNC(all, TLBIALL)
288DEFINE_TLBIOP_FUNC(allis, TLBIALLIS)
289DEFINE_TLBIOP_PARAM_FUNC(mva, TLBIMVA)
290DEFINE_TLBIOP_PARAM_FUNC(mvaa, TLBIMVAA)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000291DEFINE_TLBIOP_PARAM_FUNC(mvaais, TLBIMVAAIS)
292
293/*
294 * BPI operation prototypes.
295 */
296DEFINE_BPIOP_FUNC(allis, BPIALLIS)
Soby Mathewc6820d12016-05-09 17:49:55 +0100297
298/*
299 * DC operation prototypes
300 */
301DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC)
302DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC)
303DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
304
305/* Previously defined accessor functions with incomplete register names */
306#define dsb() dsbsy()
Etienne Carrierea2579862017-11-05 22:57:29 +0100307#define dmb() dmbsy()
Soby Mathewc6820d12016-05-09 17:49:55 +0100308
309#define IS_IN_SECURE() \
310 (GET_NS_BIT(read_scr()) == 0)
311
312 /*
313 * If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3
314 */
315#define IS_IN_EL3() \
316 ((GET_M32(read_cpsr()) == MODE32_mon) || \
317 (IS_IN_SECURE() && (GET_M32(read_cpsr()) != MODE32_usr)))
318
319/* Macros for compatibility with AArch64 system registers */
320#define read_mpidr_el1() read_mpidr()
321
322#define read_scr_el3() read_scr()
323#define write_scr_el3(_v) write_scr(_v)
324
325#define read_hcr_el2() read_hcr()
326#define write_hcr_el2(_v) write_hcr(_v)
327
328#define read_cpacr_el1() read_cpacr()
329#define write_cpacr_el1(_v) write_cpacr(_v)
330
331#define read_cntfrq_el0() read_cntfrq()
332#define write_cntfrq_el0(_v) write_cntfrq(_v)
333#define read_isr_el1() read_isr()
334
335#define read_cntpct_el0() read64_cntpct()
336
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100337#define read_ctr_el0() read_ctr()
338
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100339#define write_icc_sgi0r_el1(_v) \
340 write64_icc_sgi0r_el1(_v)
341
Soby Mathewc6820d12016-05-09 17:49:55 +0100342#endif /* __ARCH_HELPERS_H__ */