blob: e652a59ec631459983d4830f56897caa53854483 [file] [log] [blame]
Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Antonio Nino Diaze40306b2017-01-13 15:03:07 +00002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
7#ifndef __ARCH_HELPERS_H__
8#define __ARCH_HELPERS_H__
9
10#include <arch.h> /* for additional register definitions */
11#include <stdint.h>
Antonio Nino Diaze40306b2017-01-13 15:03:07 +000012#include <sys/types.h>
Soby Mathewc6820d12016-05-09 17:49:55 +010013
14/**********************************************************************
15 * Macros which create inline functions to read or write CPU system
16 * registers
17 *********************************************************************/
18
19#define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
20static inline void write_## _name(u_register_t v) \
21{ \
22 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
23}
24
25#define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
26static inline u_register_t read_ ## _name(void) \
27{ \
28 u_register_t v; \
29 __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\
30 return v; \
31}
32
33/*
34 * The undocumented %Q and %R extended asm are used to implemented the below
35 * 64 bit `mrrc` and `mcrr` instructions. It works only on Little Endian
36 * systems for GCC versions < 4.6. Above GCC 4.6, both Little Endian and
37 * Big Endian systems generate the right instruction encoding.
38 */
dp-arm320e8442017-05-02 12:00:08 +010039#if !(__clang__ || __GNUC__ > (4) || __GNUC__ == (4) && __GNUC_MINOR__ >= (6))
40#error "clang or GCC 4.6 or above is required to build AArch32 Trusted Firmware"
Soby Mathewc6820d12016-05-09 17:49:55 +010041#endif
42
43#define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \
44static inline void write64_## _name(uint64_t v) \
45{ \
46 __asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\
47}
48
49#define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \
50static inline uint64_t read64_## _name(void) \
51{ uint64_t v; \
52 __asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\
53 return v; \
54}
55
56#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
57static inline u_register_t read_ ## _name(void) \
58{ \
59 u_register_t v; \
60 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
61 return v; \
62}
63
64#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
65static inline void write_ ## _name(u_register_t v) \
66{ \
67 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
68}
69
70#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \
71static inline void write_ ## _name(const u_register_t v) \
72{ \
73 __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \
74}
75
76/* Define read function for coproc register */
77#define DEFINE_COPROCR_READ_FUNC(_name, ...) \
78 _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__)
79
80/* Define read & write function for coproc register */
81#define DEFINE_COPROCR_RW_FUNCS(_name, ...) \
82 _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) \
83 _DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__)
84
85/* Define 64 bit read function for coproc register */
86#define DEFINE_COPROCR_READ_FUNC_64(_name, ...) \
87 _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__)
88
89/* Define 64 bit read & write function for coproc register */
90#define DEFINE_COPROCR_RW_FUNCS_64(_name, ...) \
91 _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) \
92 _DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__)
93
94/* Define read & write function for system register */
95#define DEFINE_SYSREG_RW_FUNCS(_name) \
96 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
97 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
98
99/**********************************************************************
100 * Macros to create inline functions for tlbi operations
101 *********************************************************************/
102
103#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
104static inline void tlbi##_op(void) \
105{ \
106 u_register_t v = 0; \
107 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
108}
109
Antonio Nino Diazac998032017-02-27 17:23:54 +0000110#define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
111static inline void bpi##_op(void) \
112{ \
113 u_register_t v = 0; \
114 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
115}
116
Soby Mathewc6820d12016-05-09 17:49:55 +0100117#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
118static inline void tlbi##_op(u_register_t v) \
119{ \
120 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
121}
122
123/* Define function for simple TLBI operation */
124#define DEFINE_TLBIOP_FUNC(_op, ...) \
125 _DEFINE_TLBIOP_FUNC(_op, __VA_ARGS__)
126
127/* Define function for TLBI operation with register parameter */
128#define DEFINE_TLBIOP_PARAM_FUNC(_op, ...) \
129 _DEFINE_TLBIOP_PARAM_FUNC(_op, __VA_ARGS__)
130
Antonio Nino Diazac998032017-02-27 17:23:54 +0000131/* Define function for simple BPI operation */
132#define DEFINE_BPIOP_FUNC(_op, ...) \
133 _DEFINE_BPIOP_FUNC(_op, __VA_ARGS__)
134
Soby Mathewc6820d12016-05-09 17:49:55 +0100135/**********************************************************************
136 * Macros to create inline functions for DC operations
137 *********************************************************************/
138#define _DEFINE_DCOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
139static inline void dc##_op(u_register_t v) \
140{ \
141 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
142}
143
144/* Define function for DC operation with register parameter */
145#define DEFINE_DCOP_PARAM_FUNC(_op, ...) \
146 _DEFINE_DCOP_PARAM_FUNC(_op, __VA_ARGS__)
147
148/**********************************************************************
149 * Macros to create inline functions for system instructions
150 *********************************************************************/
151 /* Define function for simple system instruction */
152#define DEFINE_SYSOP_FUNC(_op) \
153static inline void _op(void) \
154{ \
155 __asm__ (#_op); \
156}
157
158
159/* Define function for system instruction with type specifier */
160#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
161static inline void _op ## _type(void) \
162{ \
163 __asm__ (#_op " " #_type); \
164}
165
166/* Define function for system instruction with register parameter */
167#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
168static inline void _op ## _type(u_register_t v) \
169{ \
170 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
171}
172
173void flush_dcache_range(uintptr_t addr, size_t size);
174void clean_dcache_range(uintptr_t addr, size_t size);
175void inv_dcache_range(uintptr_t addr, size_t size);
176
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000177void dcsw_op_louis(u_register_t op_type);
178void dcsw_op_all(u_register_t op_type);
179
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100180void disable_mmu_secure(void);
181void disable_mmu_icache_secure(void);
182
Soby Mathewc6820d12016-05-09 17:49:55 +0100183DEFINE_SYSOP_FUNC(wfi)
184DEFINE_SYSOP_FUNC(wfe)
185DEFINE_SYSOP_FUNC(sev)
186DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
187DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000188DEFINE_SYSOP_TYPE_FUNC(dmb, st)
189DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Soby Mathewc6820d12016-05-09 17:49:55 +0100190DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000191DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Soby Mathewc6820d12016-05-09 17:49:55 +0100192DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
193DEFINE_SYSOP_FUNC(isb)
194
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100195void __dead2 smc(uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3,
196 uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7);
197
Soby Mathewc6820d12016-05-09 17:49:55 +0100198DEFINE_SYSREG_RW_FUNCS(spsr)
199DEFINE_SYSREG_RW_FUNCS(cpsr)
200
201/*******************************************************************************
202 * System register accessor prototypes
203 ******************************************************************************/
204DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR)
205DEFINE_COPROCR_READ_FUNC(midr, MIDR)
206DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
207DEFINE_COPROCR_READ_FUNC(isr, ISR)
208DEFINE_COPROCR_READ_FUNC(clidr, CLIDR)
209DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64)
210
211DEFINE_COPROCR_RW_FUNCS(scr, SCR)
212DEFINE_COPROCR_RW_FUNCS(ctr, CTR)
213DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR)
214DEFINE_COPROCR_RW_FUNCS(hsctlr, HSCTLR)
215DEFINE_COPROCR_RW_FUNCS(hcr, HCR)
216DEFINE_COPROCR_RW_FUNCS(hcptr, HCPTR)
217DEFINE_COPROCR_RW_FUNCS(cntfrq, CNTFRQ)
218DEFINE_COPROCR_RW_FUNCS(cnthctl, CNTHCTL)
219DEFINE_COPROCR_RW_FUNCS(mair0, MAIR0)
220DEFINE_COPROCR_RW_FUNCS(mair1, MAIR1)
221DEFINE_COPROCR_RW_FUNCS(ttbcr, TTBCR)
222DEFINE_COPROCR_RW_FUNCS(ttbr0, TTBR0)
223DEFINE_COPROCR_RW_FUNCS_64(ttbr0, TTBR0_64)
224DEFINE_COPROCR_RW_FUNCS(ttbr1, TTBR1)
225DEFINE_COPROCR_RW_FUNCS(vpidr, VPIDR)
226DEFINE_COPROCR_RW_FUNCS(vmpidr, VMPIDR)
227DEFINE_COPROCR_RW_FUNCS_64(vttbr, VTTBR_64)
228DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64)
229DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64)
230DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR)
231
232DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE)
233DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE)
234DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE)
235DEFINE_COPROCR_RW_FUNCS(icc_pmr_el1, ICC_PMR)
236DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el3, ICC_MGRPEN1)
237DEFINE_COPROCR_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0)
238DEFINE_COPROCR_RW_FUNCS(icc_hppir0_el1, ICC_HPPIR0)
239DEFINE_COPROCR_RW_FUNCS(icc_hppir1_el1, ICC_HPPIR1)
240DEFINE_COPROCR_RW_FUNCS(icc_iar0_el1, ICC_IAR0)
241DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1)
242DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0)
243DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
244
David Cunado5f55e282016-10-31 17:37:34 +0000245DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
David Cunadoc14b08e2016-11-25 00:21:59 +0000246DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL)
David Cunado5f55e282016-10-31 17:37:34 +0000247DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
248
Soby Mathewc6820d12016-05-09 17:49:55 +0100249/*
250 * TLBI operation prototypes
251 */
252DEFINE_TLBIOP_FUNC(all, TLBIALL)
253DEFINE_TLBIOP_FUNC(allis, TLBIALLIS)
254DEFINE_TLBIOP_PARAM_FUNC(mva, TLBIMVA)
255DEFINE_TLBIOP_PARAM_FUNC(mvaa, TLBIMVAA)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000256DEFINE_TLBIOP_PARAM_FUNC(mvaais, TLBIMVAAIS)
257
258/*
259 * BPI operation prototypes.
260 */
261DEFINE_BPIOP_FUNC(allis, BPIALLIS)
Soby Mathewc6820d12016-05-09 17:49:55 +0100262
263/*
264 * DC operation prototypes
265 */
266DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC)
267DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC)
268DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
269
270/* Previously defined accessor functions with incomplete register names */
271#define dsb() dsbsy()
272
273#define IS_IN_SECURE() \
274 (GET_NS_BIT(read_scr()) == 0)
275
276 /*
277 * If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3
278 */
279#define IS_IN_EL3() \
280 ((GET_M32(read_cpsr()) == MODE32_mon) || \
281 (IS_IN_SECURE() && (GET_M32(read_cpsr()) != MODE32_usr)))
282
283/* Macros for compatibility with AArch64 system registers */
284#define read_mpidr_el1() read_mpidr()
285
286#define read_scr_el3() read_scr()
287#define write_scr_el3(_v) write_scr(_v)
288
289#define read_hcr_el2() read_hcr()
290#define write_hcr_el2(_v) write_hcr(_v)
291
292#define read_cpacr_el1() read_cpacr()
293#define write_cpacr_el1(_v) write_cpacr(_v)
294
295#define read_cntfrq_el0() read_cntfrq()
296#define write_cntfrq_el0(_v) write_cntfrq(_v)
297#define read_isr_el1() read_isr()
298
299#define read_cntpct_el0() read64_cntpct()
300
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100301#define read_ctr_el0() read_ctr()
302
Soby Mathewc6820d12016-05-09 17:49:55 +0100303#endif /* __ARCH_HELPERS_H__ */