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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Nicolas Le Bayon8ce825f2021-05-18 10:01:30 +02002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_DEF_H
8#define STM32MP1_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010011#include <drivers/st/stm32mp1_rcc.h>
12#include <dt-bindings/clock/stm32mp1-clks.h>
13#include <dt-bindings/reset/stm32mp1-resets.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils_def.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020016
Julius Werner53456fc2019-07-09 13:49:11 -070017#ifndef __ASSEMBLER__
Yann Gautier091eab52019-06-04 18:06:34 +020018#include <drivers/st/bsec.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010019#include <drivers/st/stm32mp1_clk.h>
20
Yann Gautier57e282b2019-01-07 11:17:24 +010021#include <boot_api.h>
Lionel Debieve7bd96f42019-09-03 12:22:23 +020022#include <stm32mp_auth.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010023#include <stm32mp_common.h>
24#include <stm32mp_dt.h>
Yann Gautierc7374052019-06-04 18:02:37 +020025#include <stm32mp1_dbgmcu.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010026#include <stm32mp1_private.h>
Etienne Carriere316d6342019-12-02 10:08:48 +010027#include <stm32mp1_shared_resources.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010028#endif
29
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020030#if !STM32MP_USE_STM32IMAGE
31#include "stm32mp1_fip_def.h"
32#else /* STM32MP_USE_STM32IMAGE */
33#include "stm32mp1_stm32image_def.h"
34#endif /* STM32MP_USE_STM32IMAGE */
35
Yann Gautier4b0c72a2018-07-16 10:54:09 +020036/*******************************************************************************
Yann Gautierc7374052019-06-04 18:02:37 +020037 * CHIP ID
38 ******************************************************************************/
Yann Gautiera0a6ff62021-05-10 16:05:18 +020039#define STM32MP1_CHIP_ID U(0x500)
40
Yann Gautierc7374052019-06-04 18:02:37 +020041#define STM32MP157C_PART_NB U(0x05000000)
42#define STM32MP157A_PART_NB U(0x05000001)
43#define STM32MP153C_PART_NB U(0x05000024)
44#define STM32MP153A_PART_NB U(0x05000025)
45#define STM32MP151C_PART_NB U(0x0500002E)
46#define STM32MP151A_PART_NB U(0x0500002F)
Lionel Debieve7b64e3e2019-05-17 16:01:18 +020047#define STM32MP157F_PART_NB U(0x05000080)
48#define STM32MP157D_PART_NB U(0x05000081)
49#define STM32MP153F_PART_NB U(0x050000A4)
50#define STM32MP153D_PART_NB U(0x050000A5)
51#define STM32MP151F_PART_NB U(0x050000AE)
52#define STM32MP151D_PART_NB U(0x050000AF)
Yann Gautierc7374052019-06-04 18:02:37 +020053
54#define STM32MP1_REV_B U(0x2000)
Lionel Debieve2d64b532019-06-25 10:40:37 +020055#define STM32MP1_REV_Z U(0x2001)
Yann Gautierc7374052019-06-04 18:02:37 +020056
57/*******************************************************************************
58 * PACKAGE ID
59 ******************************************************************************/
60#define PKG_AA_LFBGA448 U(4)
61#define PKG_AB_LFBGA354 U(3)
62#define PKG_AC_TFBGA361 U(2)
63#define PKG_AD_TFBGA257 U(1)
64
65/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +020066 * STM32MP1 memory map related constants
67 ******************************************************************************/
Lionel Debieve7bd96f42019-09-03 12:22:23 +020068#define STM32MP_ROM_BASE U(0x00000000)
69#define STM32MP_ROM_SIZE U(0x00020000)
Yann Gautier3c93a252021-09-15 15:12:57 +020070#define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020071
Yann Gautiera2e2a302019-02-14 11:13:39 +010072#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
73#define STM32MP_SYSRAM_SIZE U(0x00040000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020074
Etienne Carriere72369b12019-12-08 08:17:56 +010075#define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
76#define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
77 STM32MP_SYSRAM_SIZE - \
78 STM32MP_NS_SYSRAM_SIZE)
79
Etienne Carriere34f0e932020-07-16 17:36:18 +020080#define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
81#define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
82
Etienne Carriere72369b12019-12-08 08:17:56 +010083#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
84#define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
85 STM32MP_NS_SYSRAM_SIZE)
86
Yann Gautier4b0c72a2018-07-16 10:54:09 +020087/* DDR configuration */
Yann Gautiera2e2a302019-02-14 11:13:39 +010088#define STM32MP_DDR_BASE U(0xC0000000)
89#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020090
91/* DDR power initializations */
Julius Werner53456fc2019-07-09 13:49:11 -070092#ifndef __ASSEMBLER__
Yann Gautier4b0c72a2018-07-16 10:54:09 +020093enum ddr_type {
94 STM32MP_DDR3,
95 STM32MP_LPDDR2,
Yann Gautier917a00c2019-04-16 16:20:58 +020096 STM32MP_LPDDR3
Yann Gautier4b0c72a2018-07-16 10:54:09 +020097};
98#endif
99
100/* Section used inside TF binaries */
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200101#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200102/* 256 Octets reserved for header */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100103#define STM32MP_HEADER_SIZE U(0x00000100)
Yann Gautiera1ee9ed2020-09-17 11:30:18 +0200104/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
105#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200106
Etienne Carriere72369b12019-12-08 08:17:56 +0100107#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100108 STM32MP_PARAM_LOAD_SIZE + \
109 STM32MP_HEADER_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200110
Etienne Carriere72369b12019-12-08 08:17:56 +0100111#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100112 (STM32MP_PARAM_LOAD_SIZE + \
113 STM32MP_HEADER_SIZE))
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200114
Yann Gautierebc765f2020-01-16 18:50:51 +0100115/* BL2 and BL32/sp_min require finer granularity tables */
116#if defined(IMAGE_BL2)
117#define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */
118#endif
119
120#if defined(IMAGE_BL32)
121#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
122#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200123
124/*
125 * MAX_MMAP_REGIONS is usually:
126 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
127 */
Yann Gautier9d135e42018-07-16 19:36:06 +0200128#if defined(IMAGE_BL2)
Yann Gautierebc765f2020-01-16 18:50:51 +0100129 #if STM32MP_USB_PROGRAMMER
130 #define MAX_MMAP_REGIONS 8
131 #else
132 #define MAX_MMAP_REGIONS 7
133 #endif
Yann Gautier9d135e42018-07-16 19:36:06 +0200134#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200135
Yann Gautiera2e2a302019-02-14 11:13:39 +0100136#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200137#define STM32MP_BL33_MAX_SIZE U(0x400000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200138
Lionel Debieve402a46b2019-11-04 12:28:15 +0100139/* Define maximum page size for NAND devices */
140#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
141
142/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200143 * STM32MP1 device/io map related constants (used for MMU)
144 ******************************************************************************/
145#define STM32MP1_DEVICE1_BASE U(0x40000000)
146#define STM32MP1_DEVICE1_SIZE U(0x40000000)
147
148#define STM32MP1_DEVICE2_BASE U(0x80000000)
149#define STM32MP1_DEVICE2_SIZE U(0x40000000)
150
151/*******************************************************************************
152 * STM32MP1 RCC
153 ******************************************************************************/
154#define RCC_BASE U(0x50000000)
155
156/*******************************************************************************
157 * STM32MP1 PWR
158 ******************************************************************************/
159#define PWR_BASE U(0x50001000)
160
161/*******************************************************************************
Yann Gautier038bff22019-01-17 19:17:47 +0100162 * STM32MP1 GPIO
163 ******************************************************************************/
164#define GPIOA_BASE U(0x50002000)
165#define GPIOB_BASE U(0x50003000)
166#define GPIOC_BASE U(0x50004000)
167#define GPIOD_BASE U(0x50005000)
168#define GPIOE_BASE U(0x50006000)
169#define GPIOF_BASE U(0x50007000)
170#define GPIOG_BASE U(0x50008000)
171#define GPIOH_BASE U(0x50009000)
172#define GPIOI_BASE U(0x5000A000)
173#define GPIOJ_BASE U(0x5000B000)
174#define GPIOK_BASE U(0x5000C000)
175#define GPIOZ_BASE U(0x54004000)
176#define GPIO_BANK_OFFSET U(0x1000)
177
178/* Bank IDs used in GPIO driver API */
179#define GPIO_BANK_A U(0)
180#define GPIO_BANK_B U(1)
181#define GPIO_BANK_C U(2)
182#define GPIO_BANK_D U(3)
183#define GPIO_BANK_E U(4)
184#define GPIO_BANK_F U(5)
185#define GPIO_BANK_G U(6)
186#define GPIO_BANK_H U(7)
187#define GPIO_BANK_I U(8)
188#define GPIO_BANK_J U(9)
189#define GPIO_BANK_K U(10)
190#define GPIO_BANK_Z U(25)
191
192#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
193
194/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200195 * STM32MP1 UART
196 ******************************************************************************/
197#define USART1_BASE U(0x5C000000)
198#define USART2_BASE U(0x4000E000)
199#define USART3_BASE U(0x4000F000)
200#define UART4_BASE U(0x40010000)
201#define UART5_BASE U(0x40011000)
202#define USART6_BASE U(0x44003000)
203#define UART7_BASE U(0x40018000)
204#define UART8_BASE U(0x40019000)
Yann Gautiera2e2a302019-02-14 11:13:39 +0100205#define STM32MP_UART_BAUDRATE U(115200)
Yann Gautier038bff22019-01-17 19:17:47 +0100206
207/* For UART crash console */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100208#define STM32MP_DEBUG_USART_BASE UART4_BASE
Yann Gautier038bff22019-01-17 19:17:47 +0100209/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100210#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
Yann Gautier038bff22019-01-17 19:17:47 +0100211#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
212#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
213#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
214#define DEBUG_UART_TX_GPIO_PORT 11
215#define DEBUG_UART_TX_GPIO_ALTERNATE 6
216#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
217#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
218#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
219#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
Yann Gautier5c84e742020-09-14 17:21:59 +0200220#define DEBUG_UART_RST_REG RCC_APB1RSTSETR
221#define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200222
223/*******************************************************************************
Etienne Carrieree96162e2020-04-10 11:32:54 +0200224 * STM32MP1 ETZPC
225 ******************************************************************************/
226#define STM32MP1_ETZPC_BASE U(0x5C007000)
227
228/* ETZPC TZMA IDs */
229#define STM32MP1_ETZPC_TZMA_ROM U(0)
230#define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
231
232#define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
233
234/* ETZPC DECPROT IDs */
235#define STM32MP1_ETZPC_STGENC_ID 0
236#define STM32MP1_ETZPC_BKPSRAM_ID 1
237#define STM32MP1_ETZPC_IWDG1_ID 2
238#define STM32MP1_ETZPC_USART1_ID 3
239#define STM32MP1_ETZPC_SPI6_ID 4
240#define STM32MP1_ETZPC_I2C4_ID 5
241#define STM32MP1_ETZPC_RNG1_ID 7
242#define STM32MP1_ETZPC_HASH1_ID 8
243#define STM32MP1_ETZPC_CRYP1_ID 9
244#define STM32MP1_ETZPC_DDRCTRL_ID 10
245#define STM32MP1_ETZPC_DDRPHYC_ID 11
246#define STM32MP1_ETZPC_I2C6_ID 12
247#define STM32MP1_ETZPC_SEC_ID_LIMIT 13
248
249#define STM32MP1_ETZPC_TIM2_ID 16
250#define STM32MP1_ETZPC_TIM3_ID 17
251#define STM32MP1_ETZPC_TIM4_ID 18
252#define STM32MP1_ETZPC_TIM5_ID 19
253#define STM32MP1_ETZPC_TIM6_ID 20
254#define STM32MP1_ETZPC_TIM7_ID 21
255#define STM32MP1_ETZPC_TIM12_ID 22
256#define STM32MP1_ETZPC_TIM13_ID 23
257#define STM32MP1_ETZPC_TIM14_ID 24
258#define STM32MP1_ETZPC_LPTIM1_ID 25
259#define STM32MP1_ETZPC_WWDG1_ID 26
260#define STM32MP1_ETZPC_SPI2_ID 27
261#define STM32MP1_ETZPC_SPI3_ID 28
262#define STM32MP1_ETZPC_SPDIFRX_ID 29
263#define STM32MP1_ETZPC_USART2_ID 30
264#define STM32MP1_ETZPC_USART3_ID 31
265#define STM32MP1_ETZPC_UART4_ID 32
266#define STM32MP1_ETZPC_UART5_ID 33
267#define STM32MP1_ETZPC_I2C1_ID 34
268#define STM32MP1_ETZPC_I2C2_ID 35
269#define STM32MP1_ETZPC_I2C3_ID 36
270#define STM32MP1_ETZPC_I2C5_ID 37
271#define STM32MP1_ETZPC_CEC_ID 38
272#define STM32MP1_ETZPC_DAC_ID 39
273#define STM32MP1_ETZPC_UART7_ID 40
274#define STM32MP1_ETZPC_UART8_ID 41
275#define STM32MP1_ETZPC_MDIOS_ID 44
276#define STM32MP1_ETZPC_TIM1_ID 48
277#define STM32MP1_ETZPC_TIM8_ID 49
278#define STM32MP1_ETZPC_USART6_ID 51
279#define STM32MP1_ETZPC_SPI1_ID 52
280#define STM32MP1_ETZPC_SPI4_ID 53
281#define STM32MP1_ETZPC_TIM15_ID 54
282#define STM32MP1_ETZPC_TIM16_ID 55
283#define STM32MP1_ETZPC_TIM17_ID 56
284#define STM32MP1_ETZPC_SPI5_ID 57
285#define STM32MP1_ETZPC_SAI1_ID 58
286#define STM32MP1_ETZPC_SAI2_ID 59
287#define STM32MP1_ETZPC_SAI3_ID 60
288#define STM32MP1_ETZPC_DFSDM_ID 61
289#define STM32MP1_ETZPC_TT_FDCAN_ID 62
290#define STM32MP1_ETZPC_LPTIM2_ID 64
291#define STM32MP1_ETZPC_LPTIM3_ID 65
292#define STM32MP1_ETZPC_LPTIM4_ID 66
293#define STM32MP1_ETZPC_LPTIM5_ID 67
294#define STM32MP1_ETZPC_SAI4_ID 68
295#define STM32MP1_ETZPC_VREFBUF_ID 69
296#define STM32MP1_ETZPC_DCMI_ID 70
297#define STM32MP1_ETZPC_CRC2_ID 71
298#define STM32MP1_ETZPC_ADC_ID 72
299#define STM32MP1_ETZPC_HASH2_ID 73
300#define STM32MP1_ETZPC_RNG2_ID 74
301#define STM32MP1_ETZPC_CRYP2_ID 75
302#define STM32MP1_ETZPC_SRAM1_ID 80
303#define STM32MP1_ETZPC_SRAM2_ID 81
304#define STM32MP1_ETZPC_SRAM3_ID 82
305#define STM32MP1_ETZPC_SRAM4_ID 83
306#define STM32MP1_ETZPC_RETRAM_ID 84
307#define STM32MP1_ETZPC_OTG_ID 85
308#define STM32MP1_ETZPC_SDMMC3_ID 86
309#define STM32MP1_ETZPC_DLYBSD3_ID 87
310#define STM32MP1_ETZPC_DMA1_ID 88
311#define STM32MP1_ETZPC_DMA2_ID 89
312#define STM32MP1_ETZPC_DMAMUX_ID 90
313#define STM32MP1_ETZPC_FMC_ID 91
314#define STM32MP1_ETZPC_QSPI_ID 92
315#define STM32MP1_ETZPC_DLYBQ_ID 93
316#define STM32MP1_ETZPC_ETH_ID 94
317#define STM32MP1_ETZPC_RSV_ID 95
318
319#define STM32MP_ETZPC_MAX_ID 96
320
321/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200322 * STM32MP1 TZC (TZ400)
323 ******************************************************************************/
324#define STM32MP1_TZC_BASE U(0x5C006000)
325
Yann Gautier2f974232020-09-17 12:25:05 +0200326#define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
327 TZC_400_REGION_ATTR_FILTER_BIT(1))
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200328
329/*******************************************************************************
330 * STM32MP1 SDMMC
331 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +0100332#define STM32MP_SDMMC1_BASE U(0x58005000)
333#define STM32MP_SDMMC2_BASE U(0x58007000)
334#define STM32MP_SDMMC3_BASE U(0x48004000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200335
Yann Gautier4baf5822019-05-09 13:25:52 +0200336#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
337#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
338#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
339#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
340#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200341
342/*******************************************************************************
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100343 * STM32MP1 BSEC / OTP
344 ******************************************************************************/
345#define STM32MP1_OTP_MAX_ID 0x5FU
346#define STM32MP1_UPPER_OTP_START 0x20U
347
348#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
349
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100350/* OTP labels */
351#define CFG0_OTP "cfg0_otp"
352#define PART_NUMBER_OTP "part_number_otp"
353#define PACKAGE_OTP "package_otp"
354#define HW2_OTP "hw2_otp"
355#define NAND_OTP "nand_otp"
Yann Gautier5c1dab32019-04-17 15:12:58 +0200356#define MONOTONIC_OTP "monotonic_otp"
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100357#define UID_OTP "uid_otp"
358#define BOARD_ID_OTP "board_id"
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100359
360/* OTP mask */
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100361/* CFG0 */
362#define CFG0_CLOSED_DEVICE BIT(6)
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100363
Yann Gautierc7374052019-06-04 18:02:37 +0200364/* PART NUMBER */
365#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
366#define PART_NUMBER_OTP_PART_SHIFT 0
367
368/* PACKAGE */
369#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
370#define PACKAGE_OTP_PKG_SHIFT 27
371
Yann Gautier091eab52019-06-04 18:06:34 +0200372/* IWDG OTP */
373#define HW2_OTP_IWDG_HW_POS U(3)
374#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
375#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
376
Yann Gautier3edc7c32019-05-20 19:17:08 +0200377/* HW2 OTP */
378#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
379
Lionel Debieve402a46b2019-11-04 12:28:15 +0100380/* NAND OTP */
381/* NAND parameter storage flag */
382#define NAND_PARAM_STORED_IN_OTP BIT(31)
383
384/* NAND page size in bytes */
385#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
386#define NAND_PAGE_SIZE_SHIFT 29
387#define NAND_PAGE_SIZE_2K U(0)
388#define NAND_PAGE_SIZE_4K U(1)
389#define NAND_PAGE_SIZE_8K U(2)
390
391/* NAND block size in pages */
392#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
393#define NAND_BLOCK_SIZE_SHIFT 27
394#define NAND_BLOCK_SIZE_64_PAGES U(0)
395#define NAND_BLOCK_SIZE_128_PAGES U(1)
396#define NAND_BLOCK_SIZE_256_PAGES U(2)
397
398/* NAND number of block (in unit of 256 blocs) */
399#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
400#define NAND_BLOCK_NB_SHIFT 19
401#define NAND_BLOCK_NB_UNIT U(256)
402
403/* NAND bus width in bits */
404#define NAND_WIDTH_MASK BIT(18)
405#define NAND_WIDTH_SHIFT 18
406
407/* NAND number of ECC bits per 512 bytes */
408#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
409#define NAND_ECC_BIT_NB_SHIFT 15
410#define NAND_ECC_BIT_NB_UNSET U(0)
411#define NAND_ECC_BIT_NB_1_BITS U(1)
412#define NAND_ECC_BIT_NB_4_BITS U(2)
413#define NAND_ECC_BIT_NB_8_BITS U(3)
414#define NAND_ECC_ON_DIE U(4)
415
Lionel Debieve186b0462019-09-24 18:30:12 +0200416/* NAND number of planes */
417#define NAND_PLANE_BIT_NB_MASK BIT(14)
418
Yann Gautier5c1dab32019-04-17 15:12:58 +0200419/* MONOTONIC OTP */
420#define MAX_MONOTONIC_VALUE 32
421
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200422/* UID OTP */
423#define UID_WORD_NB U(3)
424
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100425/*******************************************************************************
Yann Gautier41934662018-07-20 11:36:05 +0200426 * STM32MP1 TAMP
427 ******************************************************************************/
428#define TAMP_BASE U(0x5C00A000)
429#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
430
Julius Werner53456fc2019-07-09 13:49:11 -0700431#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
Nicolas Toromanoffbb82b1b2022-02-09 12:26:31 +0100432static inline uintptr_t tamp_bkpr(uint32_t idx)
Yann Gautier41934662018-07-20 11:36:05 +0200433{
434 return TAMP_BKP_REGISTER_BASE + (idx << 2);
435}
436#endif
437
438/*******************************************************************************
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200439 * STM32MP1 USB
440 ******************************************************************************/
441#define USB_OTG_BASE U(0x49000000)
442
443/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200444 * STM32MP1 DDRCTRL
445 ******************************************************************************/
446#define DDRCTRL_BASE U(0x5A003000)
447
448/*******************************************************************************
449 * STM32MP1 DDRPHYC
450 ******************************************************************************/
451#define DDRPHYC_BASE U(0x5A004000)
452
453/*******************************************************************************
Yann Gautier091eab52019-06-04 18:06:34 +0200454 * STM32MP1 IWDG
455 ******************************************************************************/
456#define IWDG_MAX_INSTANCE U(2)
457#define IWDG1_INST U(0)
458#define IWDG2_INST U(1)
459
460#define IWDG1_BASE U(0x5C003000)
461#define IWDG2_BASE U(0x5A002000)
462
463/*******************************************************************************
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200464 * Miscellaneous STM32MP1 peripherals base address
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200465 ******************************************************************************/
Yann Gautiera18f61b2020-05-05 17:58:40 +0200466#define BSEC_BASE U(0x5C005000)
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200467#define CRYP1_BASE U(0x54001000)
Yann Gautier091eab52019-06-04 18:06:34 +0200468#define DBGMCU_BASE U(0x50081000)
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200469#define HASH1_BASE U(0x54002000)
470#define I2C4_BASE U(0x5C002000)
471#define I2C6_BASE U(0x5c009000)
472#define RNG1_BASE U(0x54003000)
473#define RTC_BASE U(0x5c004000)
474#define SPI6_BASE U(0x5c001000)
Yann Gautiera18f61b2020-05-05 17:58:40 +0200475#define STGEN_BASE U(0x5c008000)
476#define SYSCFG_BASE U(0x50020000)
Yann Gautier091eab52019-06-04 18:06:34 +0200477
478/*******************************************************************************
Yann Gautierb1279e72021-12-15 13:16:15 +0100479 * REGULATORS
480 ******************************************************************************/
481/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
482#define PLAT_NB_RDEVS U(19)
Pascal Pailletfc7b8052021-01-29 14:48:49 +0100483/* 1 FIXED */
484#define PLAT_NB_FIXED_REGS U(1)
Yann Gautierb1279e72021-12-15 13:16:15 +0100485
486/*******************************************************************************
Yann Gautier4d429472019-02-14 11:15:20 +0100487 * Device Tree defines
488 ******************************************************************************/
Yann Gautier35dc0772019-05-13 18:34:48 +0200489#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
Nicolas Le Bayon8ce825f2021-05-18 10:01:30 +0200490#define DT_DDR_COMPAT "st,stm32mp1-ddr"
Yann Gautier091eab52019-06-04 18:06:34 +0200491#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
Nicolas Le Bayone4ac5582019-09-10 10:26:50 +0200492#define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout"
Yann Gautier4ede20a2020-09-18 15:04:14 +0200493#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
Yann Gautier4d429472019-02-14 11:15:20 +0100494#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
Lionel Debieve3c0fbfe2020-12-15 10:35:59 +0100495#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure"
Yann Gautier4d429472019-02-14 11:15:20 +0100496
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200497#endif /* STM32MP1_DEF_H */