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Jiafei Panb4ccced2022-01-20 17:40:16 +08001#
2# Copyright 2022 NXP
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6#
7#------------------------------------------------------------------------------
8#
9# This file contains the basic architecture definitions that drive the build
10#
11# -----------------------------------------------------------------------------
12
13CORE_TYPE := a72
14
15CACHE_LINE := 6
16
17# set to GIC400 or GIC500
18GIC := GIC400
19
20# set to CCI400 or CCN504 or CCN508
21INTERCONNECT := CCI400
22
23# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
24CHASSIS := 2
25
26# TZC IP Details TZC used is TZC380 or TZC400
27TZC_ID := TZC400
28
29# CONSOLE Details available is NS16550 or PL011
30CONSOLE := NS16550
31
32 # Select the DDR PHY generation to be used
33PLAT_DDR_PHY := PHY_GEN1
34
35PHYS_SYS := 64
36
37# ddr controller - set to MMDC or NXP
38DDRCNTLR := NXP
39
40# ddr phy - set to NXP or SNPS
41DDRPHY := NXP
42
43# Area of OCRAM reserved by ROM code
44NXP_ROM_RSVD := 0x5900
45
46# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
47# Input to CST create_hdr_esbc tool
48CSF_HDR_SZ := 0x3000
49
50# In IMAGE_BL2, compile time flag for handling Cache coherency
51# with CAAM for BL2 running from OCRAM
52SEC_MEM_NON_COHERENT := yes
53
54# OCRAM MAP
55OCRAM_START_ADDR := 0x10000000
56OCRAM_SIZE := 0x20000
57
58# BL2 binary is placed at start of OCRAM.
59# Also used by create_pbl.mk.
60BL2_BASE := 0x10000000
61
62# After BL2 bin, OCRAM is used by ROM Code:
63# (OCRAM_START_ADDR + BL2_BIN_SIZE) -> (NXP_ROM_RSVD - 1)
64
65# After ROM Code, OCRAM is used by CSF header.
66# (OCRAM_START_ADDR + BL2_TEXT_LIMIT + NXP_ROM_RSVD) -> (CSF_HDR_SZ - 1)
67
68# BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ)
69# This value should be greater than BL2_TEXT_LIMIT
70# Input to CST create_hdr_isbc tool
71BL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(NXP_ROM_RSVD) - $(CSF_HDR_SZ))))
72# Covert to HEX to be used by create_pbl.mk
73BL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)
74
75# Core Errata
76ERRATA_A72_859971 := 1
77
78# SoC ERRATAS
79ERRATA_SOC_A008850 := 1
80ERRATA_SOC_A010539 := 1
81
82# DDR Errata
83ERRATA_DDR_A008511 := 1
84ERRATA_DDR_A009803 := 1
85ERRATA_DDR_A009942 := 1
86ERRATA_DDR_A010165 := 1
87
88# enable dynamic memory mapping
89PLAT_XLAT_TABLES_DYNAMIC := 1
90
91# Define Endianness of each module
92NXP_GUR_ENDIANNESS := BE
93NXP_DDR_ENDIANNESS := BE
94NXP_SEC_ENDIANNESS := BE
95NXP_SFP_ENDIANNESS := BE
96NXP_SNVS_ENDIANNESS := BE
97NXP_ESDHC_ENDIANNESS := BE
98NXP_QSPI_ENDIANNESS := BE
99NXP_FSPI_ENDIANNESS := BE
100NXP_SCFG_ENDIANNESS := BE
101NXP_GPIO_ENDIANNESS := BE
102NXP_IFC_ENDIANNESS := BE
103
104NXP_SFP_VER := 3_2
105
106# OCRAM ECC Enabled
107OCRAM_ECC_EN := yes