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Hadi Asyrafiab1132f2019-10-22 10:31:45 +08001/*
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +08002 * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
Hadi Asyrafiab1132f2019-10-22 10:31:45 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef SOCFPGA_SIP_SVC_H
8#define SOCFPGA_SIP_SVC_H
9
10
11/* SiP status response */
12#define INTEL_SIP_SMC_STATUS_OK 0
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080013#define INTEL_SIP_SMC_STATUS_BUSY 0x1
14#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +080015#define INTEL_SIP_SMC_STATUS_ERROR 0x4
16#define INTEL_SIP_SMC_RSU_ERROR 0x7
17
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080018
19/* SMC SiP service function identifier */
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080020
21/* FPGA Reconfig */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080022#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
23#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
24#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
25#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
26#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080027
28/* Secure Register Access */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080029#define INTEL_SIP_SMC_REG_READ 0xC2000007
30#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
31#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080032
33/* Remote System Update */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080034#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
35#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080036#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
37#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080038
39/* Send Mailbox Command */
Hadi Asyrafia33e8102019-12-17 19:30:41 +080040#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080041
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080042
43/* SiP Definitions */
44
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080045/* FPGA config helpers */
Tien Hock, Loh500b2322019-10-30 14:49:40 +080046#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
Richard Gong99b5e162020-04-13 09:40:43 -050047#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080048
49/* SMC function IDs for SiP Service queries */
50#define SIP_SVC_CALL_COUNT 0x8200ff00
51#define SIP_SVC_UID 0x8200ff01
52#define SIP_SVC_VERSION 0x8200ff03
53
54/* SiP Service Calls version numbers */
55#define SIP_SVC_VERSION_MAJOR 0
56#define SIP_SVC_VERSION_MINOR 1
57
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080058
59/* Structure Definitions */
60struct fpga_config_info {
61 uint32_t addr;
62 int size;
63 int size_written;
64 uint32_t write_requested;
65 int subblocks_sent;
66 int block_number;
67};
68
69/* Function Definitions */
70
71bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
72
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080073#endif /* SOCFPGA_SIP_SVC_H */