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git01.mediatek.com / filogic / atf / e045e1287580be4b4843d27cfe465ce9dd44b7a1 / . / plat / xilinx / versal / platform.mk
blob: 8087297a22c94df808beead2c3560c53d15ccb0e [file] [log] [blame]
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -0700[diff] [blame]1# Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]2#
3# SPDX-License-Identifier: BSD-3-Clause
4
5override PROGRAMMABLE_RESET_ADDRESS := 1
6PSCI_EXTENDED_STATE_ID := 1
7A53_DISABLE_NON_TEMPORAL_HINT := 0
8SEPARATE_CODE_AND_RODATA := 1
9override RESET_TO_BL31 := 1
10PL011_GENERIC_UART := 1
Venkatesh Yadav Abbarapu78bcd122021-02-19 01:46:21 -0700[diff] [blame]11IPI_CRC_CHECK := 0
Venkatesh Yadav Abbarapu82252a42021-07-20 22:27:32 -0600[diff] [blame]12HARDEN_SLS_ALL := 0
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]13
Michal Simek1cda4b02022-10-07 08:15:19 +0200[diff] [blame]14# A72 Erratum for SoC
15ERRATA_A72_859971 := 1
16ERRATA_A72_1319367 := 1
17
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]18ifdef VERSAL_ATF_MEM_BASE
19 $(eval $(call add_define,VERSAL_ATF_MEM_BASE))
20
21 ifndef VERSAL_ATF_MEM_SIZE
22 $(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE")
23 endif
24 $(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
25
26 ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
27 $(eval $(call add_define,VERSAL_ATF_MEM_PROGBITS_SIZE))
28 endif
29endif
30
31ifdef VERSAL_BL32_MEM_BASE
32 $(eval $(call add_define,VERSAL_BL32_MEM_BASE))
33
34 ifndef VERSAL_BL32_MEM_SIZE
35 $(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE")
36 endif
37 $(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
38endif
39
Venkatesh Yadav Abbarapu78bcd122021-02-19 01:46:21 -0700[diff] [blame]40ifdef IPI_CRC_CHECK
41 $(eval $(call add_define,IPI_CRC_CHECK))
42endif
43
Siva Durga Prasad Paladugucbc90052019-07-10 16:15:19 +0530[diff] [blame]44VERSAL_PLATFORM ?= silicon
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]45$(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM}))
46
Tejas Patel54d13192019-02-27 18:44:55 +0530[diff] [blame]47PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
48 -Iplat/xilinx/common/include/ \
Wendy Lianga4494de2019-01-21 13:45:49 +0530[diff] [blame]49 -Iplat/xilinx/common/ipi_mailbox_service/ \
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]50 -Iplat/xilinx/versal/include/ \
51 -Iplat/xilinx/versal/pm_service/
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]52
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]53# Include GICv3 driver files
54include drivers/arm/gic/v3/gicv3.mk
55
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]56PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
57 lib/xlat_tables/aarch64/xlat_tables.c \
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -0700[diff] [blame]58 drivers/arm/dcc/dcc_console.c \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]59 drivers/delay_timer/delay_timer.c \
60 drivers/delay_timer/generic_delay_timer.c \
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]61 ${GICV3_SOURCES} \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]62 drivers/arm/pl011/aarch64/pl011_console.S \
Ambroise Vincent962109f2019-03-27 13:48:15 +0000[diff] [blame]63 plat/common/aarch64/crash_console_helpers.S \
Tejas Patel54d13192019-02-27 18:44:55 +0530[diff] [blame]64 plat/arm/common/arm_cci.c \
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700[diff] [blame]65 plat/arm/common/arm_common.c \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]66 plat/common/plat_gicv3.c \
67 plat/xilinx/versal/aarch64/versal_helpers.S \
68 plat/xilinx/versal/aarch64/versal_common.c
69
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -0700[diff] [blame]70VERSAL_CONSOLE ?= pl011
71ifeq (${VERSAL_CONSOLE}, $(filter ${VERSAL_CONSOLE},pl011 pl011_0 pl011_1 dcc))
72else
73 $(error "Please define VERSAL_CONSOLE")
74endif
75
76$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
77
Tejas Patel54d13192019-02-27 18:44:55 +0530[diff] [blame]78BL31_SOURCES += drivers/arm/cci/cci.c \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]79 lib/cpus/aarch64/cortex_a72.S \
80 plat/common/plat_psci_common.c \
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]81 plat/xilinx/common/ipi.c \
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700[diff] [blame]82 plat/xilinx/common/plat_startup.c \
Wendy Lianga4494de2019-01-21 13:45:49 +0530[diff] [blame]83 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]84 plat/xilinx/common/pm_service/pm_ipi.c \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]85 plat/xilinx/versal/bl31_versal_setup.c \
86 plat/xilinx/versal/plat_psci.c \
87 plat/xilinx/versal/plat_versal.c \
88 plat/xilinx/versal/plat_topology.c \
89 plat/xilinx/versal/sip_svc_setup.c \
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]90 plat/xilinx/versal/versal_gicv3.c \
91 plat/xilinx/versal/versal_ipi.c \
92 plat/xilinx/versal/pm_service/pm_svc_main.c \
Tejas Patel9d09ff92019-01-08 01:46:35 -0800[diff] [blame]93 plat/xilinx/versal/pm_service/pm_api_sys.c \
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]94 plat/xilinx/versal/pm_service/pm_client.c
Venkatesh Yadav Abbarapu82252a42021-07-20 22:27:32 -0600[diff] [blame]95
96ifeq ($(HARDEN_SLS_ALL), 1)
97TF_CFLAGS_aarch64 += -mharden-sls=all
98endif