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Sandrine Bailleux798140d2014-07-17 16:06:39 +01001/*
dp-arm8f59e152017-02-27 12:21:43 +00002 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleux798140d2014-07-17 16:06:39 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Sandrine Bailleux798140d2014-07-17 16:06:39 +01005 */
6
7#ifndef __JUNO_DEF_H__
8#define __JUNO_DEF_H__
9
Sandrine Bailleux798140d2014-07-17 16:06:39 +010010
Sandrine Bailleux798140d2014-07-17 16:06:39 +010011/*******************************************************************************
12 * Juno memory map related constants
13 ******************************************************************************/
Sandrine Bailleuxfd8f8982015-02-04 14:06:10 +000014
15/* Board revisions */
Dan Handley7bef8002015-03-19 19:22:44 +000016#define REV_JUNO_R0 0x1 /* Rev B */
17#define REV_JUNO_R1 0x2 /* Rev C */
Sandrine Bailleux9d548a22015-11-18 11:10:30 +000018#define REV_JUNO_R2 0x3 /* Rev D */
Sandrine Bailleux798140d2014-07-17 16:06:39 +010019
Dan Handley7bef8002015-03-19 19:22:44 +000020/* Bypass offset from start of NOR flash */
21#define BL1_ROM_BYPASS_OFFSET 0x03EC0000
Sandrine Bailleux798140d2014-07-17 16:06:39 +010022
Dan Handley7bef8002015-03-19 19:22:44 +000023#define EMMC_BASE 0x0c000000
24#define EMMC_SIZE 0x04000000
Sandrine Bailleux798140d2014-07-17 16:06:39 +010025
Dan Handley7bef8002015-03-19 19:22:44 +000026#define PSRAM_BASE 0x14000000
27#define PSRAM_SIZE 0x02000000
Sandrine Bailleux798140d2014-07-17 16:06:39 +010028
Vikram Kanigirif79d1502015-11-12 17:22:16 +000029#define JUNO_SSC_VER_PART_NUM 0x030
Sandrine Bailleux798140d2014-07-17 16:06:39 +010030
31/*******************************************************************************
Soby Mathew47e43f22016-02-01 14:04:34 +000032 * Juno topology related constants
33 ******************************************************************************/
34#define JUNO_CLUSTER_COUNT 2
35#define JUNO_CLUSTER0_CORE_COUNT 2
36#define JUNO_CLUSTER1_CORE_COUNT 4
37
38/*******************************************************************************
Sandrine Bailleux798140d2014-07-17 16:06:39 +010039 * TZC-400 related constants
40 ******************************************************************************/
Dan Handley7bef8002015-03-19 19:22:44 +000041#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */
42#define TZC400_NSAID_PCIE 1
43#define TZC400_NSAID_HDLCD0 2
44#define TZC400_NSAID_HDLCD1 3
45#define TZC400_NSAID_USB 4
46#define TZC400_NSAID_DMA330 5
47#define TZC400_NSAID_THINLINKS 6
48#define TZC400_NSAID_AP 9
49#define TZC400_NSAID_GPU 10
50#define TZC400_NSAID_SCP 11
51#define TZC400_NSAID_CORESIGHT 12
Sandrine Bailleux798140d2014-07-17 16:06:39 +010052
Juan Castillo21b04192014-08-12 17:24:30 +010053/*******************************************************************************
dp-arm8f59e152017-02-27 12:21:43 +000054 * TRNG related constants
55 ******************************************************************************/
56#define TRNG_BASE 0x7FE60000ULL
57#define TRNG_NOUTPUTS 4
58#define TRNG_STATUS 0x10
59#define TRNG_INTMASK 0x14
60#define TRNG_CONFIG 0x18
61#define TRNG_CONTROL 0x1C
dp-armb3263b32017-02-28 14:43:15 +000062#define TRNG_NBYTES 16 /* Number of bytes generated per round. */
dp-arm8f59e152017-02-27 12:21:43 +000063
64/*******************************************************************************
Robin Murphy0f1d6662015-01-09 14:30:58 +000065 * MMU-401 related constants
66 ******************************************************************************/
Dan Handley7bef8002015-03-19 19:22:44 +000067#define MMU401_SSD_OFFSET 0x4000
68#define MMU401_DMA330_BASE 0x7fb00000
69
Vikram Kanigirif3bcea22015-06-24 17:51:09 +010070/*******************************************************************************
71 * Interrupt handling constants
72 ******************************************************************************/
73#define JUNO_IRQ_DMA_SMMU 126
74#define JUNO_IRQ_HDLCD0_SMMU 128
75#define JUNO_IRQ_HDLCD1_SMMU 130
76#define JUNO_IRQ_USB_SMMU 132
77#define JUNO_IRQ_THIN_LINKS_SMMU 134
78#define JUNO_IRQ_SEC_I2C 137
79#define JUNO_IRQ_GPU_SMMU_1 73
80#define JUNO_IRQ_ETR_SMMU 75
Robin Murphy0f1d6662015-01-09 14:30:58 +000081
Roberto Vargasbcca6c62018-06-11 16:15:35 +010082/*******************************************************************************
83 * Memprotect definitions
84 ******************************************************************************/
85/* PSCI memory protect definitions:
86 * This variable is stored in a non-secure flash because some ARM reference
87 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
88 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
89 */
90#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
91 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
92
Sandrine Bailleux798140d2014-07-17 16:06:39 +010093#endif /* __JUNO_DEF_H__ */