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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7c6df5b2018-01-15 14:43:42 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch.h>
8#include <arm_def.h>
Antonio Nino Diazf09d0032017-04-11 14:04:56 +01009#include <arm_xlat_tables.h>
Roberto Vargas2ca18d92018-02-12 12:36:17 +000010#include <bl1.h>
Dan Handley9df48042015-03-19 18:58:55 +000011#include <bl_common.h>
Antonio Nino Diazb37eba92018-05-15 13:12:50 +010012#include <console.h>
Dan Handley9df48042015-03-19 18:58:55 +000013#include <plat_arm.h>
Roberto Vargas2ca18d92018-02-12 12:36:17 +000014#include <platform.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010015#include <platform_def.h>
Juan Castillob6132f12015-10-06 14:01:35 +010016#include <sp805.h>
Sandrine Bailleux28ee10f2016-06-15 15:44:27 +010017#include <utils.h>
Sandrine Bailleuxd7c47502015-10-02 09:32:35 +010018#include "../../../bl1/bl1_private.h"
Dan Handley9df48042015-03-19 18:58:55 +000019
Dan Handley9df48042015-03-19 18:58:55 +000020/* Weak definitions may be overridden in specific ARM standard platform */
21#pragma weak bl1_early_platform_setup
22#pragma weak bl1_plat_arch_setup
23#pragma weak bl1_platform_setup
24#pragma weak bl1_plat_sec_mem_layout
Yatharth Kocharede39cb2016-11-14 12:01:04 +000025#pragma weak bl1_plat_prepare_exit
Dan Handley9df48042015-03-19 18:58:55 +000026
27
28/* Data structure which holds the extents of the trusted SRAM for BL1*/
29static meminfo_t bl1_tzram_layout;
30
31meminfo_t *bl1_plat_sec_mem_layout(void)
32{
33 return &bl1_tzram_layout;
34}
35
36/*******************************************************************************
37 * BL1 specific platform actions shared between ARM standard platforms.
38 ******************************************************************************/
39void arm_bl1_early_platform_setup(void)
40{
Dan Handley9df48042015-03-19 18:58:55 +000041
Juan Castillob6132f12015-10-06 14:01:35 +010042#if !ARM_DISABLE_TRUSTED_WDOG
43 /* Enable watchdog */
44 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
45#endif
46
Dan Handley9df48042015-03-19 18:58:55 +000047 /* Initialize the console to provide early debug support */
Antonio Nino Diazb37eba92018-05-15 13:12:50 +010048 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
49 ARM_CONSOLE_BAUDRATE);
Dan Handley9df48042015-03-19 18:58:55 +000050
51 /* Allow BL1 to see the whole Trusted RAM */
52 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
53 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
54
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010055#if !LOAD_IMAGE_V2
Dan Handley9df48042015-03-19 18:58:55 +000056 /* Calculate how much RAM BL1 is using and how much remains free */
57 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE;
58 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE;
59 reserve_mem(&bl1_tzram_layout.free_base,
60 &bl1_tzram_layout.free_size,
61 BL1_RAM_BASE,
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010062 BL1_RAM_LIMIT - BL1_RAM_BASE);
63#endif /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +000064}
65
66void bl1_early_platform_setup(void)
67{
68 arm_bl1_early_platform_setup();
69
70 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000071 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +000072 * No need for locks as no other CPU is active.
73 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000074 plat_arm_interconnect_init();
Dan Handley9df48042015-03-19 18:58:55 +000075 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000076 * Enable Interconnect coherency for the primary CPU's cluster.
Dan Handley9df48042015-03-19 18:58:55 +000077 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000078 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +000079}
80
81/******************************************************************************
82 * Perform the very early platform specific architecture setup shared between
83 * ARM standard platforms. This only does basic initialization. Later
84 * architectural setup (bl1_arch_setup()) does not do anything platform
85 * specific.
86 *****************************************************************************/
87void arm_bl1_plat_arch_setup(void)
88{
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010089 arm_setup_page_tables(bl1_tzram_layout.total_base,
Dan Handley9df48042015-03-19 18:58:55 +000090 bl1_tzram_layout.total_size,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010091 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +090092 BL1_CODE_END,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010093 BL1_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +090094 BL1_RO_DATA_END
Dan Handley9df48042015-03-19 18:58:55 +000095#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +090096 , BL_COHERENT_RAM_BASE,
97 BL_COHERENT_RAM_END
Dan Handley9df48042015-03-19 18:58:55 +000098#endif
99 );
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100100#ifdef AARCH32
101 enable_mmu_secure(0);
102#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100103 enable_mmu_el3(0);
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100104#endif /* AARCH32 */
Dan Handley9df48042015-03-19 18:58:55 +0000105}
106
107void bl1_plat_arch_setup(void)
108{
109 arm_bl1_plat_arch_setup();
110}
111
112/*
113 * Perform the platform specific architecture setup shared between
114 * ARM standard platforms.
115 */
116void arm_bl1_platform_setup(void)
117{
118 /* Initialise the IO layer and register platform IO devices */
119 plat_arm_io_setup();
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000120#if LOAD_IMAGE_V2
121 arm_load_tb_fw_config();
122#endif
Dan Handley9df48042015-03-19 18:58:55 +0000123}
124
125void bl1_platform_setup(void)
126{
127 arm_bl1_platform_setup();
128}
129
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000130void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
131{
Juan Castillob6132f12015-10-06 14:01:35 +0100132#if !ARM_DISABLE_TRUSTED_WDOG
133 /* Disable watchdog before leaving BL1 */
134 sp805_stop(ARM_SP805_TWDG_BASE);
135#endif
136
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000137#ifdef EL3_PAYLOAD_BASE
138 /*
139 * Program the EL3 payload's entry point address into the CPUs mailbox
140 * in order to release secondary CPUs from their holding pen and make
141 * them jump there.
142 */
143 arm_program_trusted_mailbox(ep_info->pc);
144 dsbsy();
145 sev();
146#endif
147}
Soby Mathew94273572018-03-07 11:32:04 +0000148
149/*******************************************************************************
150 * The following function checks if Firmware update is needed,
151 * by checking if TOC in FIP image is valid or not.
152 ******************************************************************************/
153unsigned int bl1_plat_get_next_image_id(void)
154{
155 if (!arm_io_is_toc_valid())
156 return NS_BL1U_IMAGE_ID;
157
158 return BL2_IMAGE_ID;
159}