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Yann Gautier66386952018-07-05 16:49:51 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
Yann Gautier2e286922019-03-11 10:04:38 +01003 * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
Yann Gautier66386952018-07-05 16:49:51 +02004 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
Yann Gautier66386952018-07-05 16:49:51 +02006/dts-v1/;
7
8#include "stm32mp157c.dtsi"
9#include "stm32mp157caa-pinctrl.dtsi"
10
11/ {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010012 model = "STMicroelectronics STM32MP157C eval daughter";
Yann Gautier66386952018-07-05 16:49:51 +020013 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
14
15 chosen {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010016 stdout-path = "serial0:115200n8";
Yann Gautier66386952018-07-05 16:49:51 +020017 };
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010018
19 aliases {
20 serial0 = &uart4;
21 };
22};
23
24&clk_hse {
25 st,digbypass;
Yann Gautier66386952018-07-05 16:49:51 +020026};
27
28&i2c4 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&i2c4_pins_a>;
31 i2c-scl-rising-time-ns = <185>;
32 i2c-scl-falling-time-ns = <20>;
33 status = "okay";
34
Yann Gautiera45433b2019-01-16 18:31:00 +010035 pmic: stpmic@33 {
36 compatible = "st,stpmic1";
Yann Gautier66386952018-07-05 16:49:51 +020037 reg = <0x33>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010038 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
Yann Gautier66386952018-07-05 16:49:51 +020041 status = "okay";
42
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010043 st,main-control-register = <0x04>;
44 st,vin-control-register = <0xc0>;
Yann Gautier990ecea2019-06-04 17:24:36 +020045 st,usb-control-register = <0x20>;
Yann Gautier66386952018-07-05 16:49:51 +020046
47 regulators {
Yann Gautiera45433b2019-01-16 18:31:00 +010048 compatible = "st,stpmic1-regulators";
Yann Gautier66386952018-07-05 16:49:51 +020049
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010050 ldo1-supply = <&v3v3>;
51 ldo2-supply = <&v3v3>;
52 ldo3-supply = <&vdd_ddr>;
53 ldo5-supply = <&v3v3>;
54 ldo6-supply = <&v3v3>;
55
56 vddcore: buck1 {
57 regulator-name = "vddcore";
Yann Gautierf3928f62019-02-14 11:15:03 +010058 regulator-min-microvolt = <1200000>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010059 regulator-max-microvolt = <1350000>;
60 regulator-always-on;
61 regulator-initial-mode = <0>;
62 regulator-over-current-protection;
63 };
64
65 vdd_ddr: buck2 {
66 regulator-name = "vdd_ddr";
67 regulator-min-microvolt = <1350000>;
68 regulator-max-microvolt = <1350000>;
69 regulator-always-on;
70 regulator-initial-mode = <0>;
71 regulator-over-current-protection;
72 };
73
74 vdd: buck3 {
75 regulator-name = "vdd";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-always-on;
79 st,mask-reset;
80 regulator-initial-mode = <0>;
81 regulator-over-current-protection;
82 };
83
Yann Gautier66386952018-07-05 16:49:51 +020084 v3v3: buck4 {
85 regulator-name = "v3v3";
86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010088 regulator-always-on;
Yann Gautier66386952018-07-05 16:49:51 +020089 regulator-over-current-protection;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010090 regulator-initial-mode = <0>;
91 };
92
93 vdda: ldo1 {
94 regulator-name = "vdda";
95 regulator-min-microvolt = <2900000>;
96 regulator-max-microvolt = <2900000>;
97 };
Yann Gautier66386952018-07-05 16:49:51 +020098
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010099 v2v8: ldo2 {
100 regulator-name = "v2v8";
101 regulator-min-microvolt = <2800000>;
102 regulator-max-microvolt = <2800000>;
Yann Gautier66386952018-07-05 16:49:51 +0200103 };
104
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100105 vtt_ddr: ldo3 {
106 regulator-name = "vtt_ddr";
107 regulator-min-microvolt = <500000>;
108 regulator-max-microvolt = <750000>;
109 regulator-always-on;
110 regulator-over-current-protection;
111 };
112
113 vdd_usb: ldo4 {
114 regulator-name = "vdd_usb";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 };
118
Yann Gautier66386952018-07-05 16:49:51 +0200119 vdd_sd: ldo5 {
120 regulator-name = "vdd_sd";
121 regulator-min-microvolt = <2900000>;
122 regulator-max-microvolt = <2900000>;
123 regulator-boot-on;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100124 };
Yann Gautier66386952018-07-05 16:49:51 +0200125
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100126 v1v8: ldo6 {
127 regulator-name = "v1v8";
128 regulator-min-microvolt = <1800000>;
129 regulator-max-microvolt = <1800000>;
130 };
131
132 vref_ddr: vref_ddr {
133 regulator-name = "vref_ddr";
134 regulator-always-on;
135 regulator-over-current-protection;
Yann Gautier66386952018-07-05 16:49:51 +0200136 };
137 };
138 };
139};
140
141&iwdg2 {
Yann Gautier66386952018-07-05 16:49:51 +0200142 timeout-sec = <32>;
143 status = "okay";
144};
145
Yann Gautier3edc7c32019-05-20 19:17:08 +0200146&pwr {
147 pwr-regulators {
148 vdd-supply = <&vdd>;
149 };
150};
151
Yann Gautier66386952018-07-05 16:49:51 +0200152&rng1 {
153 status = "okay";
154};
155
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100156&rtc {
157 status = "okay";
158};
159
Yann Gautier66386952018-07-05 16:49:51 +0200160&sdmmc1 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
163 broken-cd;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100164 st,sig-dir;
165 st,neg-edge;
166 st,use-ckin;
Yann Gautier66386952018-07-05 16:49:51 +0200167 bus-width = <4>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100168 vmmc-supply = <&vdd_sd>;
Yann Gautier66386952018-07-05 16:49:51 +0200169 sd-uhs-sdr12;
170 sd-uhs-sdr25;
171 sd-uhs-sdr50;
172 sd-uhs-ddr50;
173 sd-uhs-sdr104;
174 status = "okay";
175};
176
177&sdmmc2 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
180 non-removable;
181 no-sd;
182 no-sdio;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100183 st,neg-edge;
Yann Gautier66386952018-07-05 16:49:51 +0200184 bus-width = <8>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100185 vmmc-supply = <&v3v3>;
186 vqmmc-supply = <&v3v3>;
187 mmc-ddr-3_3v;
Yann Gautier66386952018-07-05 16:49:51 +0200188 status = "okay";
189};
190
191&uart4 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&uart4_pins_a>;
Yann Gautier66386952018-07-05 16:49:51 +0200194 status = "okay";
195};
196
197/* ATF Specific */
198#include <dt-bindings/clock/stm32mp1-clksrc.h>
199#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
Yann Gautier2e286922019-03-11 10:04:38 +0100200#include "stm32mp157c-security.dtsi"
Yann Gautier66386952018-07-05 16:49:51 +0200201
202/ {
203 aliases {
204 gpio0 = &gpioa;
205 gpio1 = &gpiob;
206 gpio2 = &gpioc;
207 gpio3 = &gpiod;
208 gpio4 = &gpioe;
209 gpio5 = &gpiof;
210 gpio6 = &gpiog;
211 gpio7 = &gpioh;
212 gpio8 = &gpioi;
213 gpio9 = &gpioj;
214 gpio10 = &gpiok;
215 gpio25 = &gpioz;
216 i2c3 = &i2c4;
217 };
Yann Gautier66386952018-07-05 16:49:51 +0200218};
219
220/* CLOCK init */
221&rcc {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100222 secure-status = "disabled";
Yann Gautier66386952018-07-05 16:49:51 +0200223 st,clksrc = <
224 CLK_MPU_PLL1P
225 CLK_AXI_PLL2P
Yann Gautiered342322019-02-15 17:33:27 +0100226 CLK_MCU_PLL3P
Yann Gautier66386952018-07-05 16:49:51 +0200227 CLK_PLL12_HSE
228 CLK_PLL3_HSE
229 CLK_PLL4_HSE
230 CLK_RTC_LSE
231 CLK_MCO1_DISABLED
232 CLK_MCO2_DISABLED
233 >;
234
235 st,clkdiv = <
236 1 /*MPU*/
237 0 /*AXI*/
Yann Gautiered342322019-02-15 17:33:27 +0100238 0 /*MCU*/
Yann Gautier66386952018-07-05 16:49:51 +0200239 1 /*APB1*/
240 1 /*APB2*/
241 1 /*APB3*/
242 1 /*APB4*/
243 2 /*APB5*/
244 23 /*RTC*/
245 0 /*MCO1*/
246 0 /*MCO2*/
247 >;
248
249 st,pkcs = <
250 CLK_CKPER_HSE
251 CLK_FMC_ACLK
252 CLK_QSPI_ACLK
253 CLK_ETH_DISABLED
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100254 CLK_SDMMC12_PLL4P
Yann Gautier66386952018-07-05 16:49:51 +0200255 CLK_DSI_DSIPLL
256 CLK_STGEN_HSE
257 CLK_USBPHY_HSE
258 CLK_SPI2S1_PLL3Q
259 CLK_SPI2S23_PLL3Q
260 CLK_SPI45_HSI
261 CLK_SPI6_HSI
262 CLK_I2C46_HSI
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100263 CLK_SDMMC3_PLL4P
Yann Gautier66386952018-07-05 16:49:51 +0200264 CLK_USBO_USBPHY
265 CLK_ADC_CKPER
266 CLK_CEC_LSE
267 CLK_I2C12_HSI
268 CLK_I2C35_HSI
269 CLK_UART1_HSI
270 CLK_UART24_HSI
271 CLK_UART35_HSI
272 CLK_UART6_HSI
273 CLK_UART78_HSI
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100274 CLK_SPDIF_PLL4P
Antonio Borneodd445ab2019-07-29 14:46:16 +0200275 CLK_FDCAN_PLL4R
Yann Gautier66386952018-07-05 16:49:51 +0200276 CLK_SAI1_PLL3Q
277 CLK_SAI2_PLL3Q
278 CLK_SAI3_PLL3Q
279 CLK_SAI4_PLL3Q
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100280 CLK_RNG1_LSI
281 CLK_RNG2_LSI
Yann Gautier66386952018-07-05 16:49:51 +0200282 CLK_LPTIM1_PCLK1
283 CLK_LPTIM23_PCLK3
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100284 CLK_LPTIM45_LSE
Yann Gautier66386952018-07-05 16:49:51 +0200285 >;
286
287 /* VCO = 1300.0 MHz => P = 650 (CPU) */
288 pll1: st,pll@0 {
289 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
290 frac = < 0x800 >;
291 };
292
293 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
294 pll2: st,pll@1 {
295 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
296 frac = < 0x1400 >;
297 };
298
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100299 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
Yann Gautier66386952018-07-05 16:49:51 +0200300 pll3: st,pll@2 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100301 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
302 frac = < 0x1a04 >;
Yann Gautier66386952018-07-05 16:49:51 +0200303 };
304
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100305 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
Yann Gautier66386952018-07-05 16:49:51 +0200306 pll4: st,pll@3 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100307 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
Yann Gautier66386952018-07-05 16:49:51 +0200308 };
309};
310
Yann Gautier990ecea2019-06-04 17:24:36 +0200311&bsec {
312 board_id: board_id@ec {
313 reg = <0xec 0x4>;
314 status = "okay";
315 secure-status = "okay";
316 };
317};