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git01.mediatek.com / filogic / atf / dd19b2e6f0c41d606c0814fed0475bf919ab8196 / . / plat / xilinx / versal / platform.mk
blob: 0b6aea029a61c1a92aec932f152a79147163b231 [file] [log] [blame]
Michal Simek2a47faa2023-04-14 08:43:51 +0200[diff] [blame]1# Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
Jay Buddhabhatti26e138a2022-12-21 23:03:35 -0800[diff] [blame]2# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5
6override PROGRAMMABLE_RESET_ADDRESS := 1
7PSCI_EXTENDED_STATE_ID := 1
8A53_DISABLE_NON_TEMPORAL_HINT := 0
9SEPARATE_CODE_AND_RODATA := 1
10override RESET_TO_BL31 := 1
11PL011_GENERIC_UART := 1
Venkatesh Yadav Abbarapu78bcd122021-02-19 01:46:21 -0700[diff] [blame]12IPI_CRC_CHECK := 0
Venkatesh Yadav Abbarapu82252a42021-07-20 22:27:32 -0600[diff] [blame]13HARDEN_SLS_ALL := 0
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]14
Michal Simek1cda4b02022-10-07 08:15:19 +0200[diff] [blame]15# A72 Erratum for SoC
16ERRATA_A72_859971 := 1
17ERRATA_A72_1319367 := 1
18
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]19ifdef VERSAL_ATF_MEM_BASE
20 $(eval $(call add_define,VERSAL_ATF_MEM_BASE))
21
22 ifndef VERSAL_ATF_MEM_SIZE
23 $(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE")
24 endif
25 $(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
26
27 ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
28 $(eval $(call add_define,VERSAL_ATF_MEM_PROGBITS_SIZE))
29 endif
30endif
31
32ifdef VERSAL_BL32_MEM_BASE
33 $(eval $(call add_define,VERSAL_BL32_MEM_BASE))
34
35 ifndef VERSAL_BL32_MEM_SIZE
36 $(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE")
37 endif
38 $(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
39endif
40
Venkatesh Yadav Abbarapu78bcd122021-02-19 01:46:21 -0700[diff] [blame]41ifdef IPI_CRC_CHECK
42 $(eval $(call add_define,IPI_CRC_CHECK))
43endif
44
Siva Durga Prasad Paladugucbc90052019-07-10 16:15:19 +0530[diff] [blame]45VERSAL_PLATFORM ?= silicon
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]46$(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM}))
47
Tejas Patel54d13192019-02-27 18:44:55 +0530[diff] [blame]48PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
49 -Iplat/xilinx/common/include/ \
Wendy Lianga4494de2019-01-21 13:45:49 +0530[diff] [blame]50 -Iplat/xilinx/common/ipi_mailbox_service/ \
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]51 -Iplat/xilinx/versal/include/ \
52 -Iplat/xilinx/versal/pm_service/
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]53
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]54# Include GICv3 driver files
55include drivers/arm/gic/v3/gicv3.mk
Michal Simek058251a2023-04-13 13:19:11 +0200[diff] [blame]56include lib/xlat_tables_v2/xlat_tables.mk
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]57
Michal Simek058251a2023-04-13 13:19:11 +0200[diff] [blame]58PLAT_BL_COMMON_SOURCES := drivers/arm/dcc/dcc_console.c \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]59 drivers/delay_timer/delay_timer.c \
60 drivers/delay_timer/generic_delay_timer.c \
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]61 ${GICV3_SOURCES} \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]62 drivers/arm/pl011/aarch64/pl011_console.S \
Ambroise Vincent962109f2019-03-27 13:48:15 +0000[diff] [blame]63 plat/common/aarch64/crash_console_helpers.S \
Tejas Patel54d13192019-02-27 18:44:55 +0530[diff] [blame]64 plat/arm/common/arm_cci.c \
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700[diff] [blame]65 plat/arm/common/arm_common.c \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]66 plat/common/plat_gicv3.c \
67 plat/xilinx/versal/aarch64/versal_helpers.S \
Michal Simek058251a2023-04-13 13:19:11 +0200[diff] [blame]68 plat/xilinx/versal/aarch64/versal_common.c \
69 ${XLAT_TABLES_LIB_SRCS}
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]70
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -0700[diff] [blame]71VERSAL_CONSOLE ?= pl011
72ifeq (${VERSAL_CONSOLE}, $(filter ${VERSAL_CONSOLE},pl011 pl011_0 pl011_1 dcc))
73else
74 $(error "Please define VERSAL_CONSOLE")
75endif
76
77$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
78
Tejas Patel54d13192019-02-27 18:44:55 +0530[diff] [blame]79BL31_SOURCES += drivers/arm/cci/cci.c \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]80 lib/cpus/aarch64/cortex_a72.S \
81 plat/common/plat_psci_common.c \
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]82 plat/xilinx/common/ipi.c \
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700[diff] [blame]83 plat/xilinx/common/plat_startup.c \
Wendy Lianga4494de2019-01-21 13:45:49 +0530[diff] [blame]84 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]85 plat/xilinx/common/pm_service/pm_ipi.c \
Jay Buddhabhatti26e138a2022-12-21 23:03:35 -0800[diff] [blame]86 plat/xilinx/common/pm_service/pm_api_sys.c \
87 plat/xilinx/common/pm_service/pm_svc_main.c \
Akshay Belsare589ccce2023-05-08 19:00:53 +0530[diff] [blame]88 plat/xilinx/common/versal.c \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530[diff] [blame]89 plat/xilinx/versal/bl31_versal_setup.c \
90 plat/xilinx/versal/plat_psci.c \
91 plat/xilinx/versal/plat_versal.c \
92 plat/xilinx/versal/plat_topology.c \
93 plat/xilinx/versal/sip_svc_setup.c \
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]94 plat/xilinx/versal/versal_gicv3.c \
95 plat/xilinx/versal/versal_ipi.c \
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]96 plat/xilinx/versal/pm_service/pm_client.c
Venkatesh Yadav Abbarapu82252a42021-07-20 22:27:32 -0600[diff] [blame]97
98ifeq ($(HARDEN_SLS_ALL), 1)
99TF_CFLAGS_aarch64 += -mharden-sls=all
100endif