Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 1 | /* |
Roberto Vargas | fecedb0 | 2018-02-01 15:19:00 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __PLATFORM_DEF_H__ |
| 8 | #define __PLATFORM_DEF_H__ |
| 9 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 10 | #include <arm_def.h> |
Antonio Nino Diaz | 9c4b1b7 | 2017-11-24 16:43:15 +0000 | [diff] [blame] | 11 | #include <arm_spm_def.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 12 | #include <board_arm_def.h> |
| 13 | #include <common_def.h> |
| 14 | #include <tzc400.h> |
Sandrine Bailleux | e32c042 | 2017-09-20 16:39:20 +0100 | [diff] [blame] | 15 | #include <utils_def.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 16 | #include <v2m_def.h> |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 17 | #include "../fvp_def.h" |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 18 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 19 | /* Required platform porting definitions */ |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 20 | #define PLATFORM_CORE_COUNT \ |
| 21 | (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) |
| 22 | |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 23 | #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 24 | PLATFORM_CORE_COUNT) + 1 |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 25 | |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 26 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 27 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 28 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 29 | * Other platform porting definitions are provided by included headers |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 30 | */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 31 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 32 | /* |
| 33 | * Required ARM standard platform porting definitions |
| 34 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 35 | #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 36 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 37 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 |
| 38 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 39 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 40 | #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 |
| 41 | #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 42 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 43 | /* No SCP in FVP */ |
David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 44 | #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 45 | |
Roberto Vargas | fecedb0 | 2018-02-01 15:19:00 +0000 | [diff] [blame] | 46 | #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 47 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 48 | /* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 49 | * Load address of BL33 for this platform port |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 50 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 51 | #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 52 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 53 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 54 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 55 | * PL011 related constants |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 56 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 57 | #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE |
| 58 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 59 | |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 60 | #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE |
| 61 | #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
| 62 | |
Dimitris Papastamos | 52323b0 | 2017-06-07 13:45:41 +0100 | [diff] [blame] | 63 | #define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE |
| 64 | #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
| 65 | |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 66 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE |
| 67 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 68 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 69 | #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE |
| 70 | #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 71 | |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 72 | #define PLAT_FVP_SMMUV3_BASE 0x2b400000 |
| 73 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 74 | /* CCI related constants */ |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 75 | #define PLAT_FVP_CCI400_BASE 0x2c090000 |
| 76 | #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 |
| 77 | #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 |
| 78 | |
| 79 | /* CCI-500/CCI-550 on Base platform */ |
| 80 | #define PLAT_FVP_CCI5XX_BASE 0x2a000000 |
| 81 | #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 |
| 82 | #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 |
Juan Castillo | e33ee5f | 2014-12-19 09:51:00 +0000 | [diff] [blame] | 83 | |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 84 | /* CCN related constants. Only CCN 502 is currently supported */ |
| 85 | #define PLAT_ARM_CCN_BASE 0x2e000000 |
| 86 | #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 |
| 87 | |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 88 | /* System timer related constants */ |
| 89 | #define PLAT_ARM_NSTIMER_FRAME_ID 1 |
| 90 | |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 91 | /* Mailbox base address */ |
| 92 | #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE |
| 93 | |
| 94 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 95 | /* TrustZone controller related constants |
| 96 | * |
| 97 | * Currently only filters 0 and 2 are connected on Base FVP. |
| 98 | * Filter 0 : CPU clusters (no access to DRAM by default) |
| 99 | * Filter 1 : not connected |
| 100 | * Filter 2 : LCDs (access to VRAM allowed by default) |
| 101 | * Filter 3 : not connected |
| 102 | * Programming unconnected filters will have no effect at the |
| 103 | * moment. These filter could, however, be connected in future. |
| 104 | * So care should be taken not to configure the unused filters. |
| 105 | * |
| 106 | * Allow only non-secure access to all DRAM to supported devices. |
| 107 | * Give access to the CPUs and Virtio. Some devices |
| 108 | * would normally use the default ID so allow that too. |
| 109 | */ |
Vikram Kanigiri | cab2f5e | 2015-07-31 14:50:36 +0100 | [diff] [blame] | 110 | #define PLAT_ARM_TZC_BASE 0x2a4a0000 |
Soby Mathew | 9c708b5 | 2016-02-26 14:23:19 +0000 | [diff] [blame] | 111 | #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 112 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 113 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 114 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ |
| 115 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ |
| 116 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ |
| 117 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ |
| 118 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 119 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 120 | /* |
| 121 | * GIC related constants to cater for both GICv2 and GICv3 instances of an |
| 122 | * FVP. They could be overriden at runtime in case the FVP implements the legacy |
| 123 | * VE memory map. |
| 124 | */ |
| 125 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 126 | #define PLAT_ARM_GICR_BASE BASE_GICR_BASE |
| 127 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 128 | |
| 129 | /* |
| 130 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 131 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 132 | * as Group 0 interrupts. |
| 133 | */ |
| 134 | #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ |
| 135 | FVP_IRQ_TZ_WDOG, \ |
| 136 | FVP_IRQ_SEC_SYS_TIMER |
| 137 | |
| 138 | #define PLAT_ARM_G0_IRQS ARM_G0_IRQS |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 139 | |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 140 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 141 | ARM_G1S_IRQ_PROPS(grp), \ |
| 142 | INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 143 | GIC_INTR_CFG_LEVEL), \ |
| 144 | INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 145 | GIC_INTR_CFG_LEVEL) |
| 146 | |
| 147 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 148 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 149 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS |
| 150 | #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS |
| 151 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 152 | #endif /* __PLATFORM_DEF_H__ */ |