Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <assert.h> |
| 34 | #include <cassert.h> |
| 35 | #include <platform_def.h> |
| 36 | #include <utils.h> |
| 37 | #include <xlat_tables_v2.h> |
| 38 | #include "../xlat_tables_private.h" |
| 39 | |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 40 | #if ENABLE_ASSERTIONS |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 41 | static unsigned long long xlat_arch_get_max_supported_pa(void) |
| 42 | { |
| 43 | /* Physical address space size for long descriptor format. */ |
| 44 | return (1ull << 40) - 1ull; |
| 45 | } |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 46 | #endif /* ENABLE_ASSERTIONS*/ |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 47 | |
| 48 | int is_mmu_enabled(void) |
| 49 | { |
| 50 | return (read_sctlr() & SCTLR_M_BIT) != 0; |
| 51 | } |
| 52 | |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 53 | #if PLAT_XLAT_TABLES_DYNAMIC |
| 54 | |
| 55 | void xlat_arch_tlbi_va(uintptr_t va) |
| 56 | { |
| 57 | /* |
| 58 | * Ensure the translation table write has drained into memory before |
| 59 | * invalidating the TLB entry. |
| 60 | */ |
| 61 | dsbishst(); |
| 62 | |
| 63 | tlbimvaais(TLBI_ADDR(va)); |
| 64 | } |
| 65 | |
| 66 | void xlat_arch_tlbi_va_sync(void) |
| 67 | { |
| 68 | /* Invalidate all entries from branch predictors. */ |
| 69 | bpiallis(); |
| 70 | |
| 71 | /* |
| 72 | * A TLB maintenance instruction can complete at any time after |
| 73 | * it is issued, but is only guaranteed to be complete after the |
| 74 | * execution of DSB by the PE that executed the TLB maintenance |
| 75 | * instruction. After the TLB invalidate instruction is |
| 76 | * complete, no new memory accesses using the invalidated TLB |
| 77 | * entries will be observed by any observer of the system |
| 78 | * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph |
| 79 | * "Ordering and completion of TLB maintenance instructions". |
| 80 | */ |
| 81 | dsbish(); |
| 82 | |
| 83 | /* |
| 84 | * The effects of a completed TLB maintenance instruction are |
| 85 | * only guaranteed to be visible on the PE that executed the |
| 86 | * instruction after the execution of an ISB instruction by the |
| 87 | * PE that executed the TLB maintenance instruction. |
| 88 | */ |
| 89 | isb(); |
| 90 | } |
| 91 | |
| 92 | #endif /* PLAT_XLAT_TABLES_DYNAMIC */ |
| 93 | |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 94 | void init_xlat_tables_arch(unsigned long long max_pa) |
| 95 | { |
| 96 | assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <= |
| 97 | xlat_arch_get_max_supported_pa()); |
| 98 | } |
| 99 | |
| 100 | /******************************************************************************* |
| 101 | * Function for enabling the MMU in Secure PL1, assuming that the |
| 102 | * page-tables have already been created. |
| 103 | ******************************************************************************/ |
| 104 | void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table) |
| 105 | |
| 106 | { |
| 107 | u_register_t mair0, ttbcr, sctlr; |
| 108 | uint64_t ttbr0; |
| 109 | |
| 110 | assert(IS_IN_SECURE()); |
| 111 | assert((read_sctlr() & SCTLR_M_BIT) == 0); |
| 112 | |
| 113 | /* Invalidate TLBs at the current exception level */ |
| 114 | tlbiall(); |
| 115 | |
| 116 | /* Set attributes in the right indices of the MAIR */ |
| 117 | mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); |
| 118 | mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, |
| 119 | ATTR_IWBWA_OWBWA_NTR_INDEX); |
| 120 | mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, |
| 121 | ATTR_NON_CACHEABLE_INDEX); |
| 122 | write_mair0(mair0); |
| 123 | |
| 124 | /* |
Summer Qin | daf5dbb | 2017-03-16 17:16:34 +0000 | [diff] [blame] | 125 | * Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1. |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 126 | */ |
Summer Qin | daf5dbb | 2017-03-16 17:16:34 +0000 | [diff] [blame] | 127 | if (flags & XLAT_TABLE_NC) { |
| 128 | /* Inner & outer non-cacheable non-shareable. */ |
| 129 | ttbcr = TTBCR_EAE_BIT | |
| 130 | TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | |
| 131 | TTBCR_RGN0_INNER_NC | |
| 132 | (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE)); |
| 133 | } else { |
| 134 | /* Inner & outer WBWA & shareable. */ |
| 135 | ttbcr = TTBCR_EAE_BIT | |
| 136 | TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | |
| 137 | TTBCR_RGN0_INNER_WBA | |
| 138 | (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE)); |
| 139 | } |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 140 | ttbcr |= TTBCR_EPD1_BIT; |
| 141 | write_ttbcr(ttbcr); |
| 142 | |
| 143 | /* Set TTBR0 bits as well */ |
| 144 | ttbr0 = (uint64_t)(uintptr_t) base_table; |
| 145 | write64_ttbr0(ttbr0); |
| 146 | write64_ttbr1(0); |
| 147 | |
| 148 | /* |
| 149 | * Ensure all translation table writes have drained |
| 150 | * into memory, the TLB invalidation is complete, |
| 151 | * and translation register writes are committed |
| 152 | * before enabling the MMU |
| 153 | */ |
| 154 | dsb(); |
| 155 | isb(); |
| 156 | |
| 157 | sctlr = read_sctlr(); |
| 158 | sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; |
| 159 | |
| 160 | if (flags & DISABLE_DCACHE) |
| 161 | sctlr &= ~SCTLR_C_BIT; |
| 162 | else |
| 163 | sctlr |= SCTLR_C_BIT; |
| 164 | |
| 165 | write_sctlr(sctlr); |
| 166 | |
| 167 | /* Ensure the MMU enable takes effect immediately */ |
| 168 | isb(); |
| 169 | } |
| 170 | |
| 171 | void enable_mmu_arch(unsigned int flags, uint64_t *base_table) |
| 172 | { |
| 173 | enable_mmu_internal_secure(flags, base_table); |
| 174 | } |