Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <assert.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 34 | #include <bl_common.h> |
| 35 | #include <bl2.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 36 | #include <debug.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 37 | #include <platform.h> |
| 38 | #include <stdio.h> |
Dan Handley | bcd60ba | 2014-04-17 18:53:42 +0100 | [diff] [blame] | 39 | #include "bl2_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
| 41 | /******************************************************************************* |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame^] | 42 | * Runs BL31 from the given entry point. It jumps to a higher exception level |
| 43 | * through an SMC. |
| 44 | ******************************************************************************/ |
| 45 | static void __dead2 bl2_run_bl31(bl31_args_t *bl2_to_bl31_args, |
| 46 | unsigned long arg1, |
| 47 | unsigned long arg2) |
| 48 | { |
| 49 | /* Set the args pointers for X0 and X1 to BL31 */ |
| 50 | bl2_to_bl31_args->bl31_image_info.args.arg0 = arg1; |
| 51 | bl2_to_bl31_args->bl31_image_info.args.arg1 = arg2; |
| 52 | |
| 53 | /* Flush the entire BL31 args buffer */ |
| 54 | flush_dcache_range((unsigned long) bl2_to_bl31_args, |
| 55 | sizeof(*bl2_to_bl31_args)); |
| 56 | |
| 57 | smc(RUN_IMAGE, (unsigned long)&bl2_to_bl31_args->bl31_image_info, |
| 58 | 0, 0, 0, 0, 0, 0); |
| 59 | } |
| 60 | |
| 61 | |
| 62 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 63 | * The only thing to do in BL2 is to load further images and pass control to |
| 64 | * BL31. The memory occupied by BL2 will be reclaimed by BL3_x stages. BL2 runs |
| 65 | * entirely in S-EL1. Since arm standard c libraries are not PIC, printf et al |
| 66 | * are not available. We rely on assertions to signal error conditions |
| 67 | ******************************************************************************/ |
| 68 | void bl2_main(void) |
| 69 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 70 | meminfo_t *bl2_tzram_layout; |
| 71 | bl31_args_t *bl2_to_bl31_args; |
Achin Gupta | a3050ed | 2014-02-19 17:52:35 +0000 | [diff] [blame] | 72 | unsigned long bl31_base, bl32_base = 0, bl33_base, el_status; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 73 | unsigned int bl2_load, bl31_load, mode; |
| 74 | |
| 75 | /* Perform remaining generic architectural setup in S-El1 */ |
| 76 | bl2_arch_setup(); |
| 77 | |
| 78 | /* Perform platform setup in BL1 */ |
| 79 | bl2_platform_setup(); |
| 80 | |
Jon Medhurst | ecf0a71 | 2014-02-17 12:18:24 +0000 | [diff] [blame] | 81 | printf("BL2 %s\n\r", build_message); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 82 | |
| 83 | /* Find out how much free trusted ram remains after BL2 load */ |
Sandrine Bailleux | ee12f6f | 2013-11-28 14:55:58 +0000 | [diff] [blame] | 84 | bl2_tzram_layout = bl2_plat_sec_mem_layout(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 85 | |
| 86 | /* |
| 87 | * Load BL31. BL1 tells BL2 whether it has been TOP or BOTTOM loaded. |
| 88 | * To avoid fragmentation of trusted SRAM memory, BL31 is always |
| 89 | * loaded opposite to BL2. This allows BL31 to reclaim BL2 memory |
| 90 | * while maintaining its free space in one contiguous chunk. |
| 91 | */ |
Sandrine Bailleux | ee12f6f | 2013-11-28 14:55:58 +0000 | [diff] [blame] | 92 | bl2_load = bl2_tzram_layout->attr & LOAD_MASK; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 93 | assert((bl2_load == TOP_LOAD) || (bl2_load == BOT_LOAD)); |
| 94 | bl31_load = (bl2_load == TOP_LOAD) ? BOT_LOAD : TOP_LOAD; |
Sandrine Bailleux | ee12f6f | 2013-11-28 14:55:58 +0000 | [diff] [blame] | 95 | bl31_base = load_image(bl2_tzram_layout, BL31_IMAGE_NAME, |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 96 | bl31_load, BL31_BASE); |
| 97 | |
| 98 | /* Assert if it has not been possible to load BL31 */ |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 99 | if (bl31_base == 0) { |
| 100 | ERROR("Failed to load BL3-1.\n"); |
| 101 | panic(); |
| 102 | } |
| 103 | |
| 104 | /* |
| 105 | * Get a pointer to the memory the platform has set aside to pass |
| 106 | * information to BL31. |
| 107 | */ |
| 108 | bl2_to_bl31_args = bl2_get_bl31_args_ptr(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 109 | |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame^] | 110 | bl2_to_bl31_args->bl31_image_info.entrypoint = bl31_base; |
| 111 | bl2_to_bl31_args->bl31_image_info.spsr = |
| 112 | SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
Achin Gupta | a3050ed | 2014-02-19 17:52:35 +0000 | [diff] [blame] | 113 | |
| 114 | /* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 115 | * Create a new layout of memory for BL31 as seen by BL2. This |
| 116 | * will gobble up all the BL2 memory. |
| 117 | */ |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 118 | init_bl31_mem_layout(bl2_tzram_layout, |
| 119 | &bl2_to_bl31_args->bl31_meminfo, |
| 120 | bl31_load); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 121 | |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 122 | /* Load the BL33 image in non-secure memory provided by the platform */ |
| 123 | bl33_base = load_image(&bl2_to_bl31_args->bl33_meminfo, |
| 124 | BL33_IMAGE_NAME, |
| 125 | BOT_LOAD, |
| 126 | plat_get_ns_image_entrypoint()); |
Harry Liebel | 561cd33 | 2014-02-14 14:42:48 +0000 | [diff] [blame] | 127 | /* Halt if failed to load normal world firmware. */ |
| 128 | if (bl33_base == 0) { |
| 129 | ERROR("Failed to load BL3-3.\n"); |
| 130 | panic(); |
| 131 | } |
| 132 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 133 | /* |
| 134 | * BL2 also needs to tell BL31 where the non-trusted software image |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 135 | * is located. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 136 | */ |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 137 | bl2_to_bl31_args->bl33_image_info.entrypoint = bl33_base; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 138 | |
| 139 | /* Figure out what mode we enter the non-secure world in */ |
| 140 | el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; |
| 141 | el_status &= ID_AA64PFR0_ELX_MASK; |
| 142 | |
| 143 | if (el_status) |
| 144 | mode = MODE_EL2; |
| 145 | else |
| 146 | mode = MODE_EL1; |
| 147 | |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 148 | /* |
| 149 | * TODO: Consider the possibility of specifying the SPSR in |
| 150 | * the FIP ToC and allowing the platform to have a say as |
| 151 | * well. |
| 152 | */ |
| 153 | bl2_to_bl31_args->bl33_image_info.spsr = |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 154 | SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 155 | bl2_to_bl31_args->bl33_image_info.security_state = NON_SECURE; |
| 156 | |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame^] | 157 | /* |
| 158 | * Load the BL32 image if there's one. It is upto to platform |
| 159 | * to specify where BL32 should be loaded if it exists. It |
| 160 | * could create space in the secure sram or point to a |
| 161 | * completely different memory. A zero size indicates that the |
| 162 | * platform does not want to load a BL32 image. |
| 163 | */ |
| 164 | if (bl2_to_bl31_args->bl32_meminfo.total_size) |
| 165 | bl32_base = load_image(&bl2_to_bl31_args->bl32_meminfo, |
| 166 | BL32_IMAGE_NAME, |
| 167 | bl2_to_bl31_args->bl32_meminfo.attr & |
| 168 | LOAD_MASK, |
| 169 | BL32_BASE); |
| 170 | |
Achin Gupta | a3050ed | 2014-02-19 17:52:35 +0000 | [diff] [blame] | 171 | if (bl32_base) { |
| 172 | /* Fill BL32 image info */ |
| 173 | bl2_to_bl31_args->bl32_image_info.entrypoint = bl32_base; |
| 174 | bl2_to_bl31_args->bl32_image_info.security_state = SECURE; |
| 175 | |
| 176 | /* |
| 177 | * The Secure Payload Dispatcher service is responsible for |
| 178 | * setting the SPSR prior to entry into the BL32 image. |
| 179 | */ |
| 180 | bl2_to_bl31_args->bl32_image_info.spsr = 0; |
| 181 | } |
| 182 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 183 | /* |
| 184 | * Run BL31 via an SMC to BL1. Information on how to pass control to |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 185 | * the BL32 (if present) and BL33 software images will be passed to |
| 186 | * BL31 as an argument. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 187 | */ |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame^] | 188 | bl2_run_bl31(bl2_to_bl31_args, (unsigned long)bl2_to_bl31_args, 0); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 189 | } |