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Konstantin Porotchkinf69ec582018-06-07 18:31:14 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8#include <arch_helpers.h>
Konstantin Porotchkind973c032018-10-02 17:45:15 +03009#include <assert.h>
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030010#include <bl_common.h>
11#include <console.h>
Konstantin Porotchkind973c032018-10-02 17:45:15 +030012#include <debug.h>
13#include <desc_image_load.h>
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030014#include <marvell_def.h>
15#include <platform_def.h>
16#include <plat_marvell.h>
17#include <string.h>
Konstantin Porotchkind973c032018-10-02 17:45:15 +030018#include <utils.h>
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030019
20/* Data structure which holds the extents of the trusted SRAM for BL2 */
21static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
22
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030023/* Weak definitions may be overridden in specific MARVELL standard platform */
Konstantin Porotchkind973c032018-10-02 17:45:15 +030024#pragma weak bl2_early_platform_setup2
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030025#pragma weak bl2_platform_setup
26#pragma weak bl2_plat_arch_setup
27#pragma weak bl2_plat_sec_mem_layout
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030028
29meminfo_t *bl2_plat_sec_mem_layout(void)
30{
31 return &bl2_tzram_layout;
32}
33
34/*****************************************************************************
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030035 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
36 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
37 * Copy it to a safe location before its reclaimed by later BL2 functionality.
38 *****************************************************************************
39 */
40void marvell_bl2_early_platform_setup(meminfo_t *mem_layout)
41{
42 /* Initialize the console to provide early debug support */
43 console_init(PLAT_MARVELL_BOOT_UART_BASE,
44 PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
45 MARVELL_CONSOLE_BAUDRATE);
46
47 /* Setup the BL2 memory layout */
48 bl2_tzram_layout = *mem_layout;
49
50 /* Initialise the IO layer and register platform IO devices */
51 plat_marvell_io_setup();
52}
53
Antonio Nino Diaz79662212018-09-24 17:15:46 +010054
55void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
56 u_register_t arg2, u_register_t arg3)
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030057{
Antonio Nino Diaz79662212018-09-24 17:15:46 +010058 struct meminfo *mem_layout = (struct meminfo *)arg1;
59
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030060 marvell_bl2_early_platform_setup(mem_layout);
61}
62
63void bl2_platform_setup(void)
64{
65 /* Nothing to do */
66}
67
68/*****************************************************************************
69 * Perform the very early platform specific architectural setup here. At the
70 * moment this is only initializes the mmu in a quick and dirty way.
71 *****************************************************************************
72 */
73void marvell_bl2_plat_arch_setup(void)
74{
75 marvell_setup_page_tables(bl2_tzram_layout.total_base,
76 bl2_tzram_layout.total_size,
77 BL_CODE_BASE,
78 BL_CODE_END,
79 BL_RO_DATA_BASE,
80 BL_RO_DATA_END
81#if USE_COHERENT_MEM
82 , BL_COHERENT_RAM_BASE,
83 BL_COHERENT_RAM_END
84#endif
85 );
86 enable_mmu_el1(0);
87}
88
89void bl2_plat_arch_setup(void)
90{
91 marvell_bl2_plat_arch_setup();
92}
93
Konstantin Porotchkind973c032018-10-02 17:45:15 +030094int marvell_bl2_handle_post_image_load(unsigned int image_id)
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030095{
Konstantin Porotchkind973c032018-10-02 17:45:15 +030096 int err = 0;
97 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030098
Konstantin Porotchkind973c032018-10-02 17:45:15 +030099 assert(bl_mem_params);
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300100
Konstantin Porotchkind973c032018-10-02 17:45:15 +0300101 switch (image_id) {
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300102
Konstantin Porotchkind973c032018-10-02 17:45:15 +0300103 case BL33_IMAGE_ID:
104 /* BL33 expects to receive the primary CPU MPID (through r0) */
105 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
106 bl_mem_params->ep_info.spsr = marvell_get_spsr_for_bl33_entry();
107 break;
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300108
Konstantin Porotchkind973c032018-10-02 17:45:15 +0300109 default:
110 /* Do nothing in default case */
111 break;
112 }
113
114 return err;
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300115
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300116}
117
Konstantin Porotchkind973c032018-10-02 17:45:15 +0300118/*******************************************************************************
119 * This function can be used by the platforms to update/use image
120 * information for given `image_id`.
121 ******************************************************************************/
122int bl2_plat_handle_post_image_load(unsigned int image_id)
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300123{
Konstantin Porotchkind973c032018-10-02 17:45:15 +0300124 return marvell_bl2_handle_post_image_load(image_id);
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300125}
Konstantin Porotchkind973c032018-10-02 17:45:15 +0300126