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Yann Gautiera3f46382023-06-14 10:40:59 +02001#
Maxime Méréc6a33f52024-12-10 10:55:58 +01002# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
Yann Gautiera3f46382023-06-14 10:40:59 +02003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Yann Gautier605facb2023-01-05 14:34:37 +01007# Extra partitions used to find FIP, contains:
8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2).
9STM32_EXTRA_PARTS := 6
10
Yann Gautiera3f46382023-06-14 10:40:59 +020011include plat/st/common/common.mk
12
13CRASH_REPORTING := 1
Maxime Méréc6a33f52024-12-10 10:55:58 +010014# Disable PIE by default. To re-enable it, uncomment next line.
15#ENABLE_PIE := 1
Yann Gautiera3f46382023-06-14 10:40:59 +020016PROGRAMMABLE_RESET_ADDRESS := 1
Maxime Méréc6a33f52024-12-10 10:55:58 +010017ifeq ($(ENABLE_PIE),1)
Yann Gautier8053f2b2024-05-21 11:46:59 +020018BL2_IN_XIP_MEM := 1
Maxime Méréc6a33f52024-12-10 10:55:58 +010019endif
Yann Gautiera3f46382023-06-14 10:40:59 +020020
Yann Gautier9542b802024-01-11 19:34:24 +010021STM32MP_BL33_EL1 ?= 1
22ifeq ($(STM32MP_BL33_EL1),1)
23INIT_UNUSED_NS_EL2 := 1
24endif
25
Yann Gautier4a952532023-10-02 09:42:50 +020026# Disable features unsupported in ARMv8.0
27ENABLE_SPE_FOR_NS := 0
28ENABLE_SVE_FOR_NS := 0
29
Yann Gautiera3f46382023-06-14 10:40:59 +020030# Default Device tree
31DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
32
Maxime Méré8b1b4872024-08-01 15:45:20 +020033TF_CFLAGS += -DSTM32MP2X
34
Yann Gautier7d6dffa2023-04-20 17:02:52 +020035STM32MP21 ?= 0
Nicolas Le Bayon48112d52024-02-02 18:28:43 +010036STM32MP23 ?= 0
Yann Gautier7d6dffa2023-04-20 17:02:52 +020037STM32MP25 ?= 0
38
39ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),)
40STM32MP21 := 1
41endif
Nicolas Le Bayon48112d52024-02-02 18:28:43 +010042ifneq ($(findstring stm32mp23,$(DTB_FILE_NAME)),)
43STM32MP23 := 1
44endif
Yann Gautier7d6dffa2023-04-20 17:02:52 +020045ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),)
Yann Gautiera3f46382023-06-14 10:40:59 +020046STM32MP25 := 1
Yann Gautier7d6dffa2023-04-20 17:02:52 +020047endif
Nicolas Le Bayon48112d52024-02-02 18:28:43 +010048ifneq ($(filter 1,$(STM32MP21) $(STM32MP23) $(STM32MP25)), 1)
Yann Gautier7d6dffa2023-04-20 17:02:52 +020049$(warning STM32MP21=$(STM32MP21))
Nicolas Le Bayon48112d52024-02-02 18:28:43 +010050$(warning STM32MP23=$(STM32MP23))
Yann Gautier7d6dffa2023-04-20 17:02:52 +020051$(warning STM32MP25=$(STM32MP25))
52$(warning DTB_FILE_NAME=$(DTB_FILE_NAME))
Nicolas Le Bayon48112d52024-02-02 18:28:43 +010053$(error Cannot enable more than one STM32MP2x flag)
Yann Gautier7d6dffa2023-04-20 17:02:52 +020054endif
Yann Gautiera3f46382023-06-14 10:40:59 +020055
Yann Gautier7d6dffa2023-04-20 17:02:52 +020056# STM32 image header version v2.2 or v2.3 for STM32MP21
Yann Gautiera3f46382023-06-14 10:40:59 +020057STM32_HEADER_VERSION_MAJOR := 2
Yann Gautier7d6dffa2023-04-20 17:02:52 +020058ifeq ($(STM32MP21),1)
59STM32_HEADER_VERSION_MINOR := 3
60else
Yann Gautiera3f46382023-06-14 10:40:59 +020061STM32_HEADER_VERSION_MINOR := 2
Yann Gautier7d6dffa2023-04-20 17:02:52 +020062endif
Yann Gautiera3f46382023-06-14 10:40:59 +020063
Yann Gautier7d13b4e2024-02-02 17:07:20 +010064# Set load address for serial boot devices
Yann Gautier8053f2b2024-05-21 11:46:59 +020065DWL_BUFFER_BASE ?= 0x87000000
Yann Gautier7d13b4e2024-02-02 17:07:20 +010066
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +020067# DDR types
68STM32MP_DDR3_TYPE ?= 0
69STM32MP_DDR4_TYPE ?= 0
70STM32MP_LPDDR4_TYPE ?= 0
71ifeq (${STM32MP_DDR3_TYPE},1)
72DDR_TYPE := ddr3
73endif
74ifeq (${STM32MP_DDR4_TYPE},1)
75DDR_TYPE := ddr4
76endif
77ifeq (${STM32MP_LPDDR4_TYPE},1)
78DDR_TYPE := lpddr4
79endif
80
Maxime Méréb151f682024-09-13 17:57:58 +020081# DDR features
Nicolas Le Bayon068d3412021-07-01 14:44:22 +020082STM32MP_DDR_DUAL_AXI_PORT := 1
Maxime Méréb151f682024-09-13 17:57:58 +020083STM32MP_DDR_FIP_IO_STORAGE := 1
84
Yann Gautier626ec9d2023-06-14 18:44:41 +020085# Device tree
86BL2_DTSI := stm32mp25-bl2.dtsi
87FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
Maxime Méré212148f2024-10-02 18:24:40 +020088BL31_DTSI := stm32mp25-bl31.dtsi
89FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME)))
Yann Gautier626ec9d2023-06-14 18:44:41 +020090
91# Macros and rules to build TF binary
92STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
93STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
94STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
95
Yann Gautier99f41322024-05-22 16:16:59 +020096STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
97STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
Maxime Méré212148f2024-10-02 18:24:40 +020098STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME)))
Maxime Méréb151f682024-09-13 17:57:58 +020099ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
100STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2
101STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin
102STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME}
103endif
Yann Gautier99f41322024-05-22 16:16:59 +0200104FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
Yann Gautier7199aad2024-11-14 09:44:44 +0100105
Yann Gautier99f41322024-05-22 16:16:59 +0200106# Add the FW_CONFIG to FIP and specify the same to certtool
107$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
Yann Gautier7199aad2024-11-14 09:44:44 +0100108
Maxime Méré212148f2024-10-02 18:24:40 +0200109# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
Yann Gautier7199aad2024-11-14 09:44:44 +0100110$(eval $(call TOOL_ADD_IMG_PAYLOAD,STM32MP_SOC_FW_CONFIG,$(STM32MP_SOC_FW_CONFIG),--soc-fw-config,$(patsubst %.dtb,%.dts,$(STM32MP_SOC_FW_CONFIG))))
111
Maxime Méréb151f682024-09-13 17:57:58 +0200112ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
113# Add the FW_DDR to FIP and specify the same to certtool
114$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
115endif
Yann Gautier99f41322024-05-22 16:16:59 +0200116
Boerge Struempfel1302eac2025-04-01 11:57:20 +0200117# Ultratronik Specific Boards
118ifeq ($(findstring ultra-fly,$(DTB_FILE_NAME)),ultra-fly)
119ULTRA_FLY := 1
120$(eval $(call assert_booleans,\
121 $(sort \
122 ULTRA_FLY \
123 )))
124$(eval $(call add_defines,\
125 $(sort \
126 ULTRA_FLY \
127 )))
128endif
129
Yann Gautier8053f2b2024-05-21 11:46:59 +0200130# Enable flags for C files
131$(eval $(call assert_booleans,\
132 $(sort \
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200133 STM32MP_DDR_DUAL_AXI_PORT \
Maxime Méréb151f682024-09-13 17:57:58 +0200134 STM32MP_DDR_FIP_IO_STORAGE \
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200135 STM32MP_DDR3_TYPE \
136 STM32MP_DDR4_TYPE \
137 STM32MP_LPDDR4_TYPE \
Yann Gautier7d6dffa2023-04-20 17:02:52 +0200138 STM32MP21 \
Nicolas Le Bayon48112d52024-02-02 18:28:43 +0100139 STM32MP23 \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200140 STM32MP25 \
Yann Gautier9542b802024-01-11 19:34:24 +0100141 STM32MP_BL33_EL1 \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200142)))
143
144$(eval $(call assert_numerics,\
145 $(sort \
146 PLAT_PARTITION_MAX_ENTRIES \
147 STM32_HEADER_VERSION_MAJOR \
148 STM32_TF_A_COPIES \
149)))
150
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100151$(eval $(call add_defines,\
152 $(sort \
153 DWL_BUFFER_BASE \
Maxime Méréb151f682024-09-13 17:57:58 +0200154 PLAT_DEF_FIP_UUID \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200155 PLAT_PARTITION_MAX_ENTRIES \
156 PLAT_TBBR_IMG_DEF \
157 STM32_TF_A_COPIES \
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200158 STM32MP_DDR_DUAL_AXI_PORT \
Maxime Méréb151f682024-09-13 17:57:58 +0200159 STM32MP_DDR_FIP_IO_STORAGE \
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200160 STM32MP_DDR3_TYPE \
161 STM32MP_DDR4_TYPE \
162 STM32MP_LPDDR4_TYPE \
Yann Gautier7d6dffa2023-04-20 17:02:52 +0200163 STM32MP21 \
Nicolas Le Bayon48112d52024-02-02 18:28:43 +0100164 STM32MP23 \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200165 STM32MP25 \
Yann Gautier9542b802024-01-11 19:34:24 +0100166 STM32MP_BL33_EL1 \
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100167)))
168
Yann Gautiera3f46382023-06-14 10:40:59 +0200169# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
170# Disable mbranch-protection to avoid adding useless code
171TF_CFLAGS += -mbranch-protection=none
172
173# Include paths and source files
174PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200175PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/
176PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/
Yann Gautiera3f46382023-06-14 10:40:59 +0200177
178PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
Yann Gautiereb91af52023-06-14 18:05:47 +0200179PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
Yann Gautiera3f46382023-06-14 10:40:59 +0200180PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
181
Pascal Paillet3263aea2022-12-16 14:59:34 +0100182PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \
183 drivers/st/pmic/stpmic2.c \
184
185PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c
186
Yann Gautier8053f2b2024-05-21 11:46:59 +0200187PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c
188
Gabriel Fernandez30437432022-04-20 10:08:08 +0200189PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \
Yann Gautierd58a3d22024-05-21 12:05:43 +0200190 drivers/st/reset/stm32mp2_reset.c \
191 plat/st/stm32mp2/stm32mp2_syscfg.c
Yann Gautiera585d762024-01-03 14:28:23 +0100192
Gabriel Fernandezbcd95062022-04-20 10:08:49 +0200193PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \
194 drivers/st/clk/clk-stm32mp2.c
195
Yann Gautiera3f46382023-06-14 10:40:59 +0200196BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
Yann Gautier8053f2b2024-05-21 11:46:59 +0200197
Pascal Paillet0e1727c2023-01-18 11:47:10 +0100198BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \
199 plat/st/stm32mp2/plat_ddr.c
Yann Gautiera3f46382023-06-14 10:40:59 +0200200
Yann Gautier8053f2b2024-05-21 11:46:59 +0200201ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
202BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c
203endif
204
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100205ifeq (${STM32MP_USB_PROGRAMMER},1)
206BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c
207endif
208
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200209BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \
210 drivers/st/ddr/stm32mp2_ddr_helpers.c \
211 drivers/st/ddr/stm32mp2_ram.c
212
213BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \
214 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \
215 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \
216 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \
217 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \
218 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \
219 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \
220 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \
221 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \
222 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \
223 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \
224 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \
225 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \
226 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c
227
228BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \
229 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \
230 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \
231 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \
232 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c
Yann Gautier40ff1382024-05-21 20:54:04 +0200233
Yann Gautierece4c252023-06-13 18:45:03 +0200234# BL31 sources
235BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
236
237BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \
238 plat/st/stm32mp2/stm32mp2_pm.c \
239 plat/st/stm32mp2/stm32mp2_topology.c
240# Generic GIC v2
241include drivers/arm/gic/v2/gicv2.mk
242
243BL31_SOURCES += ${GICV2_SOURCES} \
244 plat/common/plat_gicv2.c \
245 plat/st/common/stm32mp_gic.c
246
247# Generic PSCI
248BL31_SOURCES += plat/common/plat_psci_common.c
249
Gatien Chevallier77f2a322022-07-27 17:57:35 +0200250BL31_SOURCES += plat/st/common/stm32mp_svc_setup.c \
Gatien Chevallier24648002022-07-27 17:57:35 +0200251 plat/st/stm32mp2/services/stgen_svc.c \
Gatien Chevallier77f2a322022-07-27 17:57:35 +0200252 plat/st/stm32mp2/services/stm32mp2_svc_setup.c
253
254# Arm Archtecture services
255BL31_SOURCES += services/arm_arch_svc/arm_arch_svc_setup.c
256
Yann Gautier8053f2b2024-05-21 11:46:59 +0200257# Compilation rules
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200258.PHONY: check_ddr_type
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200259bl2: check_ddr_type
260
261check_ddr_type:
262 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \
263 $(STM32MP_DDR4_TYPE) + \
264 $(STM32MP_LPDDR4_TYPE)))))
265 @if [ ${DDR_TYPE} != 1 ]; then \
266 echo "One and only one DDR type must be defined"; \
267 false; \
268 fi
269
Maxime Méré212148f2024-10-02 18:24:40 +0200270# Create DTB file for BL31
271${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/
272 @echo '#include "$(patsubst fdts/%,%,$<)"' > $@
273 @echo '#include "${BL31_DTSI}"' >> $@
274
Yann Gautiera3f46382023-06-14 10:40:59 +0200275include plat/st/common/common_rules.mk