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Yann Gautiera3f46382023-06-14 10:40:59 +02001#
Maxime Méréc6a33f52024-12-10 10:55:58 +01002# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
Yann Gautiera3f46382023-06-14 10:40:59 +02003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Yann Gautier605facb2023-01-05 14:34:37 +01007# Extra partitions used to find FIP, contains:
8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2).
9STM32_EXTRA_PARTS := 6
10
Yann Gautiera3f46382023-06-14 10:40:59 +020011include plat/st/common/common.mk
12
13CRASH_REPORTING := 1
Maxime Méréc6a33f52024-12-10 10:55:58 +010014# Disable PIE by default. To re-enable it, uncomment next line.
15#ENABLE_PIE := 1
Yann Gautiera3f46382023-06-14 10:40:59 +020016PROGRAMMABLE_RESET_ADDRESS := 1
Maxime Méréc6a33f52024-12-10 10:55:58 +010017ifeq ($(ENABLE_PIE),1)
Yann Gautier8053f2b2024-05-21 11:46:59 +020018BL2_IN_XIP_MEM := 1
Maxime Méréc6a33f52024-12-10 10:55:58 +010019endif
Yann Gautiera3f46382023-06-14 10:40:59 +020020
Yann Gautier9542b802024-01-11 19:34:24 +010021STM32MP_BL33_EL1 ?= 1
22ifeq ($(STM32MP_BL33_EL1),1)
23INIT_UNUSED_NS_EL2 := 1
24endif
25
Yann Gautier4a952532023-10-02 09:42:50 +020026# Disable features unsupported in ARMv8.0
27ENABLE_SPE_FOR_NS := 0
28ENABLE_SVE_FOR_NS := 0
29
Yann Gautiera3f46382023-06-14 10:40:59 +020030# Default Device tree
31DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
32
Yann Gautier7d6dffa2023-04-20 17:02:52 +020033STM32MP21 ?= 0
Nicolas Le Bayon48112d52024-02-02 18:28:43 +010034STM32MP23 ?= 0
Yann Gautier7d6dffa2023-04-20 17:02:52 +020035STM32MP25 ?= 0
36
37ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),)
38STM32MP21 := 1
39endif
Nicolas Le Bayon48112d52024-02-02 18:28:43 +010040ifneq ($(findstring stm32mp23,$(DTB_FILE_NAME)),)
41STM32MP23 := 1
42endif
Yann Gautier7d6dffa2023-04-20 17:02:52 +020043ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),)
Yann Gautiera3f46382023-06-14 10:40:59 +020044STM32MP25 := 1
Yann Gautier7d6dffa2023-04-20 17:02:52 +020045endif
Nicolas Le Bayon48112d52024-02-02 18:28:43 +010046ifneq ($(filter 1,$(STM32MP21) $(STM32MP23) $(STM32MP25)), 1)
Yann Gautier7d6dffa2023-04-20 17:02:52 +020047$(warning STM32MP21=$(STM32MP21))
Nicolas Le Bayon48112d52024-02-02 18:28:43 +010048$(warning STM32MP23=$(STM32MP23))
Yann Gautier7d6dffa2023-04-20 17:02:52 +020049$(warning STM32MP25=$(STM32MP25))
50$(warning DTB_FILE_NAME=$(DTB_FILE_NAME))
Nicolas Le Bayon48112d52024-02-02 18:28:43 +010051$(error Cannot enable more than one STM32MP2x flag)
Yann Gautier7d6dffa2023-04-20 17:02:52 +020052endif
Yann Gautiera3f46382023-06-14 10:40:59 +020053
Yann Gautier7d6dffa2023-04-20 17:02:52 +020054# STM32 image header version v2.2 or v2.3 for STM32MP21
Yann Gautiera3f46382023-06-14 10:40:59 +020055STM32_HEADER_VERSION_MAJOR := 2
Yann Gautier7d6dffa2023-04-20 17:02:52 +020056ifeq ($(STM32MP21),1)
57STM32_HEADER_VERSION_MINOR := 3
58else
Yann Gautiera3f46382023-06-14 10:40:59 +020059STM32_HEADER_VERSION_MINOR := 2
Yann Gautier7d6dffa2023-04-20 17:02:52 +020060endif
Yann Gautiera3f46382023-06-14 10:40:59 +020061
Yann Gautier7d13b4e2024-02-02 17:07:20 +010062# Set load address for serial boot devices
Yann Gautier8053f2b2024-05-21 11:46:59 +020063DWL_BUFFER_BASE ?= 0x87000000
Yann Gautier7d13b4e2024-02-02 17:07:20 +010064
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +020065# DDR types
66STM32MP_DDR3_TYPE ?= 0
67STM32MP_DDR4_TYPE ?= 0
68STM32MP_LPDDR4_TYPE ?= 0
69ifeq (${STM32MP_DDR3_TYPE},1)
70DDR_TYPE := ddr3
71endif
72ifeq (${STM32MP_DDR4_TYPE},1)
73DDR_TYPE := ddr4
74endif
75ifeq (${STM32MP_LPDDR4_TYPE},1)
76DDR_TYPE := lpddr4
77endif
78
Maxime Méréb151f682024-09-13 17:57:58 +020079# DDR features
Nicolas Le Bayon068d3412021-07-01 14:44:22 +020080STM32MP_DDR_DUAL_AXI_PORT := 1
Maxime Méréb151f682024-09-13 17:57:58 +020081STM32MP_DDR_FIP_IO_STORAGE := 1
82
Yann Gautier626ec9d2023-06-14 18:44:41 +020083# Device tree
84BL2_DTSI := stm32mp25-bl2.dtsi
85FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
Maxime Méré212148f2024-10-02 18:24:40 +020086BL31_DTSI := stm32mp25-bl31.dtsi
87FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME)))
Yann Gautier626ec9d2023-06-14 18:44:41 +020088
89# Macros and rules to build TF binary
90STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
91STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
92STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
93
Yann Gautier99f41322024-05-22 16:16:59 +020094STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
95STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
Maxime Méré212148f2024-10-02 18:24:40 +020096STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME)))
Maxime Méréb151f682024-09-13 17:57:58 +020097ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
98STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2
99STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin
100STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME}
101endif
Yann Gautier99f41322024-05-22 16:16:59 +0200102FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
Yann Gautier7199aad2024-11-14 09:44:44 +0100103
Yann Gautier99f41322024-05-22 16:16:59 +0200104# Add the FW_CONFIG to FIP and specify the same to certtool
105$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
Yann Gautier7199aad2024-11-14 09:44:44 +0100106
Maxime Méré212148f2024-10-02 18:24:40 +0200107# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
Yann Gautier7199aad2024-11-14 09:44:44 +0100108$(eval $(call TOOL_ADD_IMG_PAYLOAD,STM32MP_SOC_FW_CONFIG,$(STM32MP_SOC_FW_CONFIG),--soc-fw-config,$(patsubst %.dtb,%.dts,$(STM32MP_SOC_FW_CONFIG))))
109
Maxime Méréb151f682024-09-13 17:57:58 +0200110ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
111# Add the FW_DDR to FIP and specify the same to certtool
112$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
113endif
Yann Gautier99f41322024-05-22 16:16:59 +0200114
Boerge Struempfel1302eac2025-04-01 11:57:20 +0200115# Ultratronik Specific Boards
116ifeq ($(findstring ultra-fly,$(DTB_FILE_NAME)),ultra-fly)
117ULTRA_FLY := 1
118$(eval $(call assert_booleans,\
119 $(sort \
120 ULTRA_FLY \
121 )))
122$(eval $(call add_defines,\
123 $(sort \
124 ULTRA_FLY \
125 )))
126endif
127
Yann Gautier8053f2b2024-05-21 11:46:59 +0200128# Enable flags for C files
129$(eval $(call assert_booleans,\
130 $(sort \
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200131 STM32MP_DDR_DUAL_AXI_PORT \
Maxime Méréb151f682024-09-13 17:57:58 +0200132 STM32MP_DDR_FIP_IO_STORAGE \
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200133 STM32MP_DDR3_TYPE \
134 STM32MP_DDR4_TYPE \
135 STM32MP_LPDDR4_TYPE \
Yann Gautier7d6dffa2023-04-20 17:02:52 +0200136 STM32MP21 \
Nicolas Le Bayon48112d52024-02-02 18:28:43 +0100137 STM32MP23 \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200138 STM32MP25 \
Yann Gautier9542b802024-01-11 19:34:24 +0100139 STM32MP_BL33_EL1 \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200140)))
141
142$(eval $(call assert_numerics,\
143 $(sort \
144 PLAT_PARTITION_MAX_ENTRIES \
145 STM32_HEADER_VERSION_MAJOR \
146 STM32_TF_A_COPIES \
147)))
148
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100149$(eval $(call add_defines,\
150 $(sort \
151 DWL_BUFFER_BASE \
Maxime Méréb151f682024-09-13 17:57:58 +0200152 PLAT_DEF_FIP_UUID \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200153 PLAT_PARTITION_MAX_ENTRIES \
154 PLAT_TBBR_IMG_DEF \
155 STM32_TF_A_COPIES \
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200156 STM32MP_DDR_DUAL_AXI_PORT \
Maxime Méréb151f682024-09-13 17:57:58 +0200157 STM32MP_DDR_FIP_IO_STORAGE \
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200158 STM32MP_DDR3_TYPE \
159 STM32MP_DDR4_TYPE \
160 STM32MP_LPDDR4_TYPE \
Yann Gautier7d6dffa2023-04-20 17:02:52 +0200161 STM32MP21 \
Nicolas Le Bayon48112d52024-02-02 18:28:43 +0100162 STM32MP23 \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200163 STM32MP25 \
Yann Gautier9542b802024-01-11 19:34:24 +0100164 STM32MP_BL33_EL1 \
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100165)))
166
Yann Gautiera3f46382023-06-14 10:40:59 +0200167# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
168# Disable mbranch-protection to avoid adding useless code
169TF_CFLAGS += -mbranch-protection=none
170
171# Include paths and source files
172PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200173PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/
174PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/
Yann Gautiera3f46382023-06-14 10:40:59 +0200175
176PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
Yann Gautiereb91af52023-06-14 18:05:47 +0200177PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
Yann Gautiera3f46382023-06-14 10:40:59 +0200178PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
179
Pascal Paillet3263aea2022-12-16 14:59:34 +0100180PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \
181 drivers/st/pmic/stpmic2.c \
182
183PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c
184
Yann Gautier8053f2b2024-05-21 11:46:59 +0200185PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c
186
Gabriel Fernandez30437432022-04-20 10:08:08 +0200187PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \
Yann Gautierd58a3d22024-05-21 12:05:43 +0200188 drivers/st/reset/stm32mp2_reset.c \
189 plat/st/stm32mp2/stm32mp2_syscfg.c
Yann Gautiera585d762024-01-03 14:28:23 +0100190
Gabriel Fernandezbcd95062022-04-20 10:08:49 +0200191PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \
192 drivers/st/clk/clk-stm32mp2.c
193
Yann Gautiera3f46382023-06-14 10:40:59 +0200194BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
Yann Gautier8053f2b2024-05-21 11:46:59 +0200195
Pascal Paillet0e1727c2023-01-18 11:47:10 +0100196BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \
197 plat/st/stm32mp2/plat_ddr.c
Yann Gautiera3f46382023-06-14 10:40:59 +0200198
Yann Gautier8053f2b2024-05-21 11:46:59 +0200199ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
200BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c
201endif
202
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100203ifeq (${STM32MP_USB_PROGRAMMER},1)
204BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c
205endif
206
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200207BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \
208 drivers/st/ddr/stm32mp2_ddr_helpers.c \
209 drivers/st/ddr/stm32mp2_ram.c
210
211BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \
212 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \
213 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \
214 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \
215 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \
216 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \
217 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \
218 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \
219 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \
220 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \
221 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \
222 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \
223 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \
224 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c
225
226BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \
227 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \
228 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \
229 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \
230 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c
Yann Gautier40ff1382024-05-21 20:54:04 +0200231
Yann Gautierece4c252023-06-13 18:45:03 +0200232# BL31 sources
233BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
234
235BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \
236 plat/st/stm32mp2/stm32mp2_pm.c \
237 plat/st/stm32mp2/stm32mp2_topology.c
238# Generic GIC v2
239include drivers/arm/gic/v2/gicv2.mk
240
241BL31_SOURCES += ${GICV2_SOURCES} \
242 plat/common/plat_gicv2.c \
243 plat/st/common/stm32mp_gic.c
244
245# Generic PSCI
246BL31_SOURCES += plat/common/plat_psci_common.c
247
Gatien Chevallier77f2a322022-07-27 17:57:35 +0200248BL31_SOURCES += plat/st/common/stm32mp_svc_setup.c \
Gatien Chevallier24648002022-07-27 17:57:35 +0200249 plat/st/stm32mp2/services/stgen_svc.c \
Gatien Chevallier77f2a322022-07-27 17:57:35 +0200250 plat/st/stm32mp2/services/stm32mp2_svc_setup.c
251
252# Arm Archtecture services
253BL31_SOURCES += services/arm_arch_svc/arm_arch_svc_setup.c
254
Yann Gautier8053f2b2024-05-21 11:46:59 +0200255# Compilation rules
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200256.PHONY: check_ddr_type
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200257bl2: check_ddr_type
258
259check_ddr_type:
260 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \
261 $(STM32MP_DDR4_TYPE) + \
262 $(STM32MP_LPDDR4_TYPE)))))
263 @if [ ${DDR_TYPE} != 1 ]; then \
264 echo "One and only one DDR type must be defined"; \
265 false; \
266 fi
267
Maxime Méré212148f2024-10-02 18:24:40 +0200268# Create DTB file for BL31
269${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/
270 @echo '#include "$(patsubst fdts/%,%,$<)"' > $@
271 @echo '#include "${BL31_DTSI}"' >> $@
272
Yann Gautiera3f46382023-06-14 10:40:59 +0200273include plat/st/common/common_rules.mk