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Yann Gautiera3f46382023-06-14 10:40:59 +02001#
Maxime Méréc6a33f52024-12-10 10:55:58 +01002# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
Yann Gautiera3f46382023-06-14 10:40:59 +02003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Yann Gautier605facb2023-01-05 14:34:37 +01007# Extra partitions used to find FIP, contains:
8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2).
9STM32_EXTRA_PARTS := 6
10
Yann Gautiera3f46382023-06-14 10:40:59 +020011include plat/st/common/common.mk
12
13CRASH_REPORTING := 1
Maxime Méréc6a33f52024-12-10 10:55:58 +010014# Disable PIE by default. To re-enable it, uncomment next line.
15#ENABLE_PIE := 1
Yann Gautiera3f46382023-06-14 10:40:59 +020016PROGRAMMABLE_RESET_ADDRESS := 1
Maxime Méréc6a33f52024-12-10 10:55:58 +010017ifeq ($(ENABLE_PIE),1)
Yann Gautier8053f2b2024-05-21 11:46:59 +020018BL2_IN_XIP_MEM := 1
Maxime Méréc6a33f52024-12-10 10:55:58 +010019endif
Yann Gautiera3f46382023-06-14 10:40:59 +020020
Yann Gautier9542b802024-01-11 19:34:24 +010021STM32MP_BL33_EL1 ?= 1
22ifeq ($(STM32MP_BL33_EL1),1)
23INIT_UNUSED_NS_EL2 := 1
24endif
25
Yann Gautier4a952532023-10-02 09:42:50 +020026# Disable features unsupported in ARMv8.0
27ENABLE_SPE_FOR_NS := 0
28ENABLE_SVE_FOR_NS := 0
29
Yann Gautiera3f46382023-06-14 10:40:59 +020030# Default Device tree
31DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
32
Yann Gautier7d6dffa2023-04-20 17:02:52 +020033STM32MP21 ?= 0
34STM32MP25 ?= 0
35
36ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),)
37STM32MP21 := 1
38endif
39ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),)
Yann Gautiera3f46382023-06-14 10:40:59 +020040STM32MP25 := 1
Yann Gautier7d6dffa2023-04-20 17:02:52 +020041endif
42ifneq ($(filter 1,$(STM32MP21) $(STM32MP25)), 1)
43$(warning STM32MP21=$(STM32MP21))
44$(warning STM32MP25=$(STM32MP25))
45$(warning DTB_FILE_NAME=$(DTB_FILE_NAME))
46$(error Cannot enable 2 flags STM32MP2X)
47endif
Yann Gautiera3f46382023-06-14 10:40:59 +020048
Yann Gautier7d6dffa2023-04-20 17:02:52 +020049# STM32 image header version v2.2 or v2.3 for STM32MP21
Yann Gautiera3f46382023-06-14 10:40:59 +020050STM32_HEADER_VERSION_MAJOR := 2
Yann Gautier7d6dffa2023-04-20 17:02:52 +020051ifeq ($(STM32MP21),1)
52STM32_HEADER_VERSION_MINOR := 3
53else
Yann Gautiera3f46382023-06-14 10:40:59 +020054STM32_HEADER_VERSION_MINOR := 2
Yann Gautier7d6dffa2023-04-20 17:02:52 +020055endif
Yann Gautiera3f46382023-06-14 10:40:59 +020056
Yann Gautier7d13b4e2024-02-02 17:07:20 +010057# Set load address for serial boot devices
Yann Gautier8053f2b2024-05-21 11:46:59 +020058DWL_BUFFER_BASE ?= 0x87000000
Yann Gautier7d13b4e2024-02-02 17:07:20 +010059
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +020060# DDR types
61STM32MP_DDR3_TYPE ?= 0
62STM32MP_DDR4_TYPE ?= 0
63STM32MP_LPDDR4_TYPE ?= 0
64ifeq (${STM32MP_DDR3_TYPE},1)
65DDR_TYPE := ddr3
66endif
67ifeq (${STM32MP_DDR4_TYPE},1)
68DDR_TYPE := ddr4
69endif
70ifeq (${STM32MP_LPDDR4_TYPE},1)
71DDR_TYPE := lpddr4
72endif
73
Maxime Méréb151f682024-09-13 17:57:58 +020074# DDR features
Nicolas Le Bayon068d3412021-07-01 14:44:22 +020075STM32MP_DDR_DUAL_AXI_PORT := 1
Maxime Méréb151f682024-09-13 17:57:58 +020076STM32MP_DDR_FIP_IO_STORAGE := 1
77
Yann Gautier626ec9d2023-06-14 18:44:41 +020078# Device tree
79BL2_DTSI := stm32mp25-bl2.dtsi
80FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
Maxime Méré212148f2024-10-02 18:24:40 +020081BL31_DTSI := stm32mp25-bl31.dtsi
82FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME)))
Yann Gautier626ec9d2023-06-14 18:44:41 +020083
84# Macros and rules to build TF binary
85STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
86STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
87STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
88
Yann Gautier99f41322024-05-22 16:16:59 +020089STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
90STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
Maxime Méré212148f2024-10-02 18:24:40 +020091STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME)))
Maxime Méréb151f682024-09-13 17:57:58 +020092ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
93STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2
94STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin
95STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME}
96endif
Yann Gautier99f41322024-05-22 16:16:59 +020097FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
Yann Gautier7199aad2024-11-14 09:44:44 +010098
Yann Gautier99f41322024-05-22 16:16:59 +020099# Add the FW_CONFIG to FIP and specify the same to certtool
100$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
Yann Gautier7199aad2024-11-14 09:44:44 +0100101
Maxime Méré212148f2024-10-02 18:24:40 +0200102# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
Yann Gautier7199aad2024-11-14 09:44:44 +0100103$(eval $(call TOOL_ADD_IMG_PAYLOAD,STM32MP_SOC_FW_CONFIG,$(STM32MP_SOC_FW_CONFIG),--soc-fw-config,$(patsubst %.dtb,%.dts,$(STM32MP_SOC_FW_CONFIG))))
104
Maxime Méréb151f682024-09-13 17:57:58 +0200105ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
106# Add the FW_DDR to FIP and specify the same to certtool
107$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
108endif
Yann Gautier99f41322024-05-22 16:16:59 +0200109
Boerge Struempfel1302eac2025-04-01 11:57:20 +0200110# Ultratronik Specific Boards
111ifeq ($(findstring ultra-fly,$(DTB_FILE_NAME)),ultra-fly)
112ULTRA_FLY := 1
113$(eval $(call assert_booleans,\
114 $(sort \
115 ULTRA_FLY \
116 )))
117$(eval $(call add_defines,\
118 $(sort \
119 ULTRA_FLY \
120 )))
121endif
122
Yann Gautier8053f2b2024-05-21 11:46:59 +0200123# Enable flags for C files
124$(eval $(call assert_booleans,\
125 $(sort \
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200126 STM32MP_DDR_DUAL_AXI_PORT \
Maxime Méréb151f682024-09-13 17:57:58 +0200127 STM32MP_DDR_FIP_IO_STORAGE \
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200128 STM32MP_DDR3_TYPE \
129 STM32MP_DDR4_TYPE \
130 STM32MP_LPDDR4_TYPE \
Yann Gautier7d6dffa2023-04-20 17:02:52 +0200131 STM32MP21 \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200132 STM32MP25 \
Yann Gautier9542b802024-01-11 19:34:24 +0100133 STM32MP_BL33_EL1 \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200134)))
135
136$(eval $(call assert_numerics,\
137 $(sort \
138 PLAT_PARTITION_MAX_ENTRIES \
139 STM32_HEADER_VERSION_MAJOR \
140 STM32_TF_A_COPIES \
141)))
142
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100143$(eval $(call add_defines,\
144 $(sort \
145 DWL_BUFFER_BASE \
Maxime Méréb151f682024-09-13 17:57:58 +0200146 PLAT_DEF_FIP_UUID \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200147 PLAT_PARTITION_MAX_ENTRIES \
148 PLAT_TBBR_IMG_DEF \
149 STM32_TF_A_COPIES \
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200150 STM32MP_DDR_DUAL_AXI_PORT \
Maxime Méréb151f682024-09-13 17:57:58 +0200151 STM32MP_DDR_FIP_IO_STORAGE \
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200152 STM32MP_DDR3_TYPE \
153 STM32MP_DDR4_TYPE \
154 STM32MP_LPDDR4_TYPE \
Yann Gautier7d6dffa2023-04-20 17:02:52 +0200155 STM32MP21 \
Yann Gautier8053f2b2024-05-21 11:46:59 +0200156 STM32MP25 \
Yann Gautier9542b802024-01-11 19:34:24 +0100157 STM32MP_BL33_EL1 \
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100158)))
159
Yann Gautiera3f46382023-06-14 10:40:59 +0200160# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
161# Disable mbranch-protection to avoid adding useless code
162TF_CFLAGS += -mbranch-protection=none
163
164# Include paths and source files
165PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200166PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/
167PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/
Yann Gautiera3f46382023-06-14 10:40:59 +0200168
169PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
Yann Gautiereb91af52023-06-14 18:05:47 +0200170PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
Yann Gautiera3f46382023-06-14 10:40:59 +0200171PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
172
Pascal Paillet3263aea2022-12-16 14:59:34 +0100173PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \
174 drivers/st/pmic/stpmic2.c \
175
176PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c
177
Yann Gautier8053f2b2024-05-21 11:46:59 +0200178PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c
179
Gabriel Fernandez30437432022-04-20 10:08:08 +0200180PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \
Yann Gautierd58a3d22024-05-21 12:05:43 +0200181 drivers/st/reset/stm32mp2_reset.c \
182 plat/st/stm32mp2/stm32mp2_syscfg.c
Yann Gautiera585d762024-01-03 14:28:23 +0100183
Gabriel Fernandezbcd95062022-04-20 10:08:49 +0200184PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \
185 drivers/st/clk/clk-stm32mp2.c
186
Yann Gautiera3f46382023-06-14 10:40:59 +0200187BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
Yann Gautier8053f2b2024-05-21 11:46:59 +0200188
Pascal Paillet0e1727c2023-01-18 11:47:10 +0100189BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \
190 plat/st/stm32mp2/plat_ddr.c
Yann Gautiera3f46382023-06-14 10:40:59 +0200191
Yann Gautier8053f2b2024-05-21 11:46:59 +0200192ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
193BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c
194endif
195
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100196ifeq (${STM32MP_USB_PROGRAMMER},1)
197BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c
198endif
199
Nicolas Le Bayon068d3412021-07-01 14:44:22 +0200200BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \
201 drivers/st/ddr/stm32mp2_ddr_helpers.c \
202 drivers/st/ddr/stm32mp2_ram.c
203
204BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \
205 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \
206 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \
207 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \
208 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \
209 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \
210 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \
211 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \
212 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \
213 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \
214 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \
215 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \
216 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \
217 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c
218
219BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \
220 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \
221 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \
222 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \
223 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c
Yann Gautier40ff1382024-05-21 20:54:04 +0200224
Yann Gautierece4c252023-06-13 18:45:03 +0200225# BL31 sources
226BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
227
228BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \
229 plat/st/stm32mp2/stm32mp2_pm.c \
230 plat/st/stm32mp2/stm32mp2_topology.c
231# Generic GIC v2
232include drivers/arm/gic/v2/gicv2.mk
233
234BL31_SOURCES += ${GICV2_SOURCES} \
235 plat/common/plat_gicv2.c \
236 plat/st/common/stm32mp_gic.c
237
238# Generic PSCI
239BL31_SOURCES += plat/common/plat_psci_common.c
240
Gatien Chevallier77f2a322022-07-27 17:57:35 +0200241BL31_SOURCES += plat/st/common/stm32mp_svc_setup.c \
Gatien Chevallier24648002022-07-27 17:57:35 +0200242 plat/st/stm32mp2/services/stgen_svc.c \
Gatien Chevallier77f2a322022-07-27 17:57:35 +0200243 plat/st/stm32mp2/services/stm32mp2_svc_setup.c
244
245# Arm Archtecture services
246BL31_SOURCES += services/arm_arch_svc/arm_arch_svc_setup.c
247
Yann Gautier8053f2b2024-05-21 11:46:59 +0200248# Compilation rules
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200249.PHONY: check_ddr_type
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200250bl2: check_ddr_type
251
252check_ddr_type:
253 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \
254 $(STM32MP_DDR4_TYPE) + \
255 $(STM32MP_LPDDR4_TYPE)))))
256 @if [ ${DDR_TYPE} != 1 ]; then \
257 echo "One and only one DDR type must be defined"; \
258 false; \
259 fi
260
Maxime Méré212148f2024-10-02 18:24:40 +0200261# Create DTB file for BL31
262${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/
263 @echo '#include "$(patsubst fdts/%,%,$<)"' > $@
264 @echo '#include "${BL31_DTSI}"' >> $@
265
Yann Gautiera3f46382023-06-14 10:40:59 +0200266include plat/st/common/common_rules.mk