Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 1 | /* |
Govindraj Raja | 24d3a4e | 2023-12-21 13:57:49 -0600 | [diff] [blame] | 2 | * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved. |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Andre Przywara | 5b00511 | 2022-11-14 15:38:58 +0000 | [diff] [blame] | 7 | #include <arch_features.h> |
| 8 | #include <common/debug.h> |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 9 | #include <common/feat_detect.h> |
| 10 | |
Andre Przywara | cc4118d | 2022-11-14 15:42:44 +0000 | [diff] [blame] | 11 | static bool tainted; |
| 12 | |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 13 | /******************************************************************************* |
| 14 | * This section lists the wrapper modules for each feature to evaluate the |
Andre Przywara | 5b00511 | 2022-11-14 15:38:58 +0000 | [diff] [blame] | 15 | * feature states (FEAT_STATE_ALWAYS and FEAT_STATE_CHECK) and perform |
| 16 | * necessary action as below: |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 17 | * |
| 18 | * It verifies whether the FEAT_XXX (eg: FEAT_SB) is supported by the PE or not. |
| 19 | * Without this check an exception would occur during context save/restore |
| 20 | * routines, if the feature is enabled but not supported by PE. |
| 21 | ******************************************************************************/ |
| 22 | |
Andre Przywara | 5b00511 | 2022-11-14 15:38:58 +0000 | [diff] [blame] | 23 | #define feat_detect_panic(a, b) ((a) ? (void)0 : feature_panic(b)) |
| 24 | |
| 25 | /******************************************************************************* |
| 26 | * Function : feature_panic |
| 27 | * Customised panic function with error logging mechanism to list the feature |
| 28 | * not supported by the PE. |
| 29 | ******************************************************************************/ |
| 30 | static inline void feature_panic(char *feat_name) |
| 31 | { |
| 32 | ERROR("FEAT_%s not supported by the PE\n", feat_name); |
| 33 | panic(); |
| 34 | } |
| 35 | |
Andre Przywara | cc4118d | 2022-11-14 15:42:44 +0000 | [diff] [blame] | 36 | /******************************************************************************* |
| 37 | * Function : check_feature |
| 38 | * Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and |
Andre Przywara | 2f3e79a | 2023-02-01 11:46:31 +0000 | [diff] [blame] | 39 | * feature availability on the hardware. <min> is the smallest feature |
| 40 | * ID field value that is required for that feature. |
| 41 | * Triggers a panic later if a feature is forcefully enabled, but not |
| 42 | * available on the PE. Also will panic if the hardware feature ID field |
| 43 | * is larger than the maximum known and supported number, specified by <max>. |
Andre Przywara | cc4118d | 2022-11-14 15:42:44 +0000 | [diff] [blame] | 44 | * |
| 45 | * We force inlining here to let the compiler optimise away the whole check |
| 46 | * if the feature is disabled at build time (FEAT_STATE_DISABLED). |
| 47 | ******************************************************************************/ |
| 48 | static inline void __attribute((__always_inline__)) |
Andre Przywara | 2f3e79a | 2023-02-01 11:46:31 +0000 | [diff] [blame] | 49 | check_feature(int state, unsigned long field, const char *feat_name, |
| 50 | unsigned int min, unsigned int max) |
Andre Przywara | cc4118d | 2022-11-14 15:42:44 +0000 | [diff] [blame] | 51 | { |
Andre Przywara | 2f3e79a | 2023-02-01 11:46:31 +0000 | [diff] [blame] | 52 | if (state == FEAT_STATE_ALWAYS && field < min) { |
Andre Przywara | cc4118d | 2022-11-14 15:42:44 +0000 | [diff] [blame] | 53 | ERROR("FEAT_%s not supported by the PE\n", feat_name); |
| 54 | tainted = true; |
| 55 | } |
Andre Przywara | 2f3e79a | 2023-02-01 11:46:31 +0000 | [diff] [blame] | 56 | if (state >= FEAT_STATE_ALWAYS && field > max) { |
| 57 | ERROR("FEAT_%s is version %ld, but is only known up to version %d\n", |
| 58 | feat_name, field, max); |
| 59 | tainted = true; |
| 60 | } |
Andre Przywara | cc4118d | 2022-11-14 15:42:44 +0000 | [diff] [blame] | 61 | } |
| 62 | |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 63 | /************************************************ |
| 64 | * Feature : FEAT_PAUTH (Pointer Authentication) |
| 65 | ***********************************************/ |
| 66 | static void read_feat_pauth(void) |
| 67 | { |
Andre Przywara | 5b00511 | 2022-11-14 15:38:58 +0000 | [diff] [blame] | 68 | #if (ENABLE_PAUTH == FEAT_STATE_ALWAYS) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_ALWAYS) |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 69 | feat_detect_panic(is_armv8_3_pauth_present(), "PAUTH"); |
| 70 | #endif |
| 71 | } |
| 72 | |
Sona Mathew | d8e89d5 | 2024-04-19 00:24:18 -0500 | [diff] [blame^] | 73 | static unsigned int read_feat_rng_trap_id_field(void) |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 74 | { |
Sona Mathew | d8e89d5 | 2024-04-19 00:24:18 -0500 | [diff] [blame^] | 75 | return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, |
| 76 | ID_AA64PFR1_EL1_RNDR_TRAP_MASK); |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 77 | } |
| 78 | |
Sona Mathew | d8e89d5 | 2024-04-19 00:24:18 -0500 | [diff] [blame^] | 79 | static unsigned int read_feat_bti_id_field(void) |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 80 | { |
Sona Mathew | d8e89d5 | 2024-04-19 00:24:18 -0500 | [diff] [blame^] | 81 | return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT, |
| 82 | ID_AA64PFR1_EL1_BT_MASK); |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 83 | } |
| 84 | |
Sona Mathew | d8e89d5 | 2024-04-19 00:24:18 -0500 | [diff] [blame^] | 85 | static unsigned int read_feat_sb_id_field(void) |
Juan Pablo Conde | 42305f2 | 2022-07-12 16:40:29 -0400 | [diff] [blame] | 86 | { |
Sona Mathew | d8e89d5 | 2024-04-19 00:24:18 -0500 | [diff] [blame^] | 87 | return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT, |
| 88 | ID_AA64ISAR1_SB_MASK); |
Juan Pablo Conde | 42305f2 | 2022-07-12 16:40:29 -0400 | [diff] [blame] | 89 | } |
| 90 | |
Sona Mathew | d8e89d5 | 2024-04-19 00:24:18 -0500 | [diff] [blame^] | 91 | static unsigned int read_feat_csv2_id_field(void) |
| 92 | { |
| 93 | return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT, |
| 94 | ID_AA64PFR0_CSV2_MASK); |
| 95 | } |
| 96 | |
| 97 | static unsigned int read_feat_pmuv3_id_field(void) |
| 98 | { |
| 99 | return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT, |
| 100 | ID_AA64DFR0_PMUVER_MASK); |
| 101 | } |
| 102 | |
| 103 | static unsigned int read_feat_vhe_id_field(void) |
| 104 | { |
| 105 | return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT, |
| 106 | ID_AA64MMFR1_EL1_VHE_MASK); |
| 107 | } |
| 108 | |
| 109 | static unsigned int read_feat_sve_id_field(void) |
| 110 | { |
| 111 | return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT, |
| 112 | ID_AA64PFR0_SVE_MASK); |
| 113 | } |
| 114 | |
| 115 | static unsigned int read_feat_ras_id_field(void) |
| 116 | { |
| 117 | return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT, |
| 118 | ID_AA64PFR0_RAS_MASK); |
| 119 | } |
| 120 | |
| 121 | static unsigned int read_feat_dit_id_field(void) |
| 122 | { |
| 123 | return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT, |
| 124 | ID_AA64PFR0_DIT_MASK); |
| 125 | } |
| 126 | |
| 127 | static unsigned int read_feat_amu_id_field(void) |
| 128 | { |
| 129 | return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT, |
| 130 | ID_AA64PFR0_AMU_MASK); |
| 131 | } |
| 132 | |
| 133 | static unsigned int read_feat_mpam_version(void) |
| 134 | { |
| 135 | return (unsigned int)((((read_id_aa64pfr0_el1() >> |
| 136 | ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | |
| 137 | ((read_id_aa64pfr1_el1() >> |
| 138 | ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); |
| 139 | } |
| 140 | |
| 141 | static unsigned int read_feat_nv_id_field(void) |
| 142 | { |
| 143 | return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT, |
| 144 | ID_AA64MMFR2_EL1_NV_MASK); |
| 145 | } |
| 146 | |
| 147 | static unsigned int read_feat_sel2_id_field(void) |
| 148 | { |
| 149 | return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT, |
| 150 | ID_AA64PFR0_SEL2_MASK); |
| 151 | } |
| 152 | |
| 153 | static unsigned int read_feat_trf_id_field(void) |
| 154 | { |
| 155 | return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT, |
| 156 | ID_AA64DFR0_TRACEFILT_MASK); |
| 157 | } |
| 158 | static unsigned int get_armv8_5_mte_support(void) |
| 159 | { |
| 160 | return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT, |
| 161 | ID_AA64PFR1_EL1_MTE_MASK); |
| 162 | } |
| 163 | static unsigned int read_feat_rng_id_field(void) |
| 164 | { |
| 165 | return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT, |
| 166 | ID_AA64ISAR0_RNDR_MASK); |
| 167 | } |
| 168 | static unsigned int read_feat_fgt_id_field(void) |
| 169 | { |
| 170 | return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT, |
| 171 | ID_AA64MMFR0_EL1_FGT_MASK); |
| 172 | } |
| 173 | static unsigned int read_feat_ecv_id_field(void) |
| 174 | { |
| 175 | return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT, |
| 176 | ID_AA64MMFR0_EL1_ECV_MASK); |
| 177 | } |
| 178 | static unsigned int read_feat_twed_id_field(void) |
| 179 | { |
| 180 | return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT, |
| 181 | ID_AA64MMFR1_EL1_TWED_MASK); |
| 182 | } |
| 183 | |
| 184 | static unsigned int read_feat_hcx_id_field(void) |
| 185 | { |
| 186 | return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT, |
| 187 | ID_AA64MMFR1_EL1_HCX_MASK); |
| 188 | } |
| 189 | static unsigned int read_feat_tcr2_id_field(void) |
| 190 | { |
| 191 | return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT, |
| 192 | ID_AA64MMFR3_EL1_TCRX_MASK); |
| 193 | } |
| 194 | static unsigned int read_feat_s2pie_id_field(void) |
| 195 | { |
| 196 | return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT, |
| 197 | ID_AA64MMFR3_EL1_S2PIE_MASK); |
| 198 | } |
| 199 | static unsigned int read_feat_s1pie_id_field(void) |
| 200 | { |
| 201 | return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT, |
| 202 | ID_AA64MMFR3_EL1_S1PIE_MASK); |
| 203 | } |
| 204 | static unsigned int read_feat_s2poe_id_field(void) |
| 205 | { |
| 206 | return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT, |
| 207 | ID_AA64MMFR3_EL1_S2POE_MASK); |
| 208 | } |
| 209 | static unsigned int read_feat_s1poe_id_field(void) |
| 210 | { |
| 211 | return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT, |
| 212 | ID_AA64MMFR3_EL1_S1POE_MASK); |
| 213 | } |
| 214 | static unsigned int read_feat_brbe_id_field(void) |
| 215 | { |
| 216 | return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT, |
| 217 | ID_AA64DFR0_BRBE_MASK); |
| 218 | } |
| 219 | static unsigned int read_feat_trbe_id_field(void) |
| 220 | { |
| 221 | return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT, |
| 222 | ID_AA64DFR0_TRACEBUFFER_MASK); |
| 223 | } |
| 224 | static unsigned int read_feat_sme_id_field(void) |
| 225 | { |
| 226 | return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT, |
| 227 | ID_AA64PFR1_EL1_SME_MASK); |
| 228 | } |
| 229 | static unsigned int read_feat_gcs_id_field(void) |
| 230 | { |
| 231 | return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT, |
| 232 | ID_AA64PFR1_EL1_GCS_MASK); |
| 233 | } |
| 234 | |
| 235 | static unsigned int read_feat_rme_id_field(void) |
| 236 | { |
| 237 | return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT, |
| 238 | ID_AA64PFR0_FEAT_RME_MASK); |
| 239 | } |
| 240 | |
| 241 | static unsigned int read_feat_pan_id_field(void) |
| 242 | { |
| 243 | return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT, |
| 244 | ID_AA64MMFR1_EL1_PAN_MASK); |
| 245 | } |
| 246 | |
| 247 | static unsigned int read_feat_mtpmu_id_field(void) |
| 248 | { |
| 249 | return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, |
| 250 | ID_AA64DFR0_MTPMU_MASK); |
| 251 | |
| 252 | } |
| 253 | |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 254 | /*********************************************************************************** |
| 255 | * TF-A supports many Arm architectural features starting from arch version |
| 256 | * (8.0 till 8.7+). These features are mostly enabled through build flags. This |
| 257 | * mechanism helps in validating these build flags in the early boot phase |
| 258 | * either in BL1 or BL31 depending on the platform and assists in identifying |
| 259 | * and notifying the features which are enabled but not supported by the PE. |
| 260 | * |
| 261 | * It reads all the enabled features ID-registers and ensures the features |
| 262 | * are supported by the PE. |
| 263 | * In case if they aren't it stops booting at an early phase and logs the error |
| 264 | * messages, notifying the platforms about the features that are not supported. |
| 265 | * |
| 266 | * Further the procedure is implemented with a tri-state approach for each feature: |
| 267 | * ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time |
| 268 | * ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware. |
| 269 | * There will be panic if feature is not present at cold boot. |
| 270 | * ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime |
| 271 | * depending on hardware capability. |
| 272 | * |
Andre Przywara | 5b00511 | 2022-11-14 15:38:58 +0000 | [diff] [blame] | 273 | * For better readability, state values are defined with macros, namely: |
| 274 | * { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values |
| 275 | * { 0, 1, 2 }, respectively, as their naming. |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 276 | **********************************************************************************/ |
| 277 | void detect_arch_features(void) |
| 278 | { |
Andre Przywara | cc4118d | 2022-11-14 15:42:44 +0000 | [diff] [blame] | 279 | tainted = false; |
| 280 | |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 281 | /* v8.0 features */ |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 282 | check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", 1, 1); |
Andre Przywara | 902c902 | 2022-11-17 17:30:43 +0000 | [diff] [blame] | 283 | check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(), |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 284 | "CSV2_2", 2, 3); |
Boyan Karatotev | 05504ba | 2023-02-15 13:21:50 +0000 | [diff] [blame] | 285 | /* |
| 286 | * Even though the PMUv3 is an OPTIONAL feature, it is always |
| 287 | * implemented and Arm prescribes so. So assume it will be there and do |
| 288 | * away with a flag for it. This is used to check minor PMUv3px |
| 289 | * revisions so that we catch them as they come along |
| 290 | */ |
| 291 | check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(), |
| 292 | "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P7); |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 293 | |
| 294 | /* v8.1 features */ |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 295 | check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3); |
Andre Przywara | 98908b3 | 2022-11-17 16:42:09 +0000 | [diff] [blame] | 296 | check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), "VHE", 1, 1); |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 297 | |
| 298 | /* v8.2 features */ |
Jayanth Dodderi Chidanand | d62c681 | 2023-03-07 10:43:19 +0000 | [diff] [blame] | 299 | check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(), |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 300 | "SVE", 1, 1); |
Andre Przywara | 870627e | 2023-01-27 12:25:49 +0000 | [diff] [blame] | 301 | check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2); |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 302 | |
| 303 | /* v8.3 features */ |
Sona Mathew | d8e89d5 | 2024-04-19 00:24:18 -0500 | [diff] [blame^] | 304 | /* TODO: Pauth yet to convert to tri-state feat detect logic */ |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 305 | read_feat_pauth(); |
| 306 | |
| 307 | /* v8.4 features */ |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 308 | check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT", 1, 1); |
Andre Przywara | 0b7f1b0 | 2023-03-21 13:53:19 +0000 | [diff] [blame] | 309 | check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(), |
Andre Przywara | 2f3e79a | 2023-02-01 11:46:31 +0000 | [diff] [blame] | 310 | "AMUv1", 1, 2); |
Arvind Ram Prakash | ab28d4b | 2023-10-11 12:10:56 -0500 | [diff] [blame] | 311 | check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(), |
Andre Przywara | a96d450 | 2023-03-21 14:44:59 +0000 | [diff] [blame] | 312 | "MPAM", 1, 17); |
Andre Przywara | edc449d | 2023-01-27 14:09:20 +0000 | [diff] [blame] | 313 | check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(), |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 314 | "NV2", 2, 2); |
Andre Przywara | 6dd2d06 | 2023-02-22 16:53:50 +0000 | [diff] [blame] | 315 | check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(), |
| 316 | "SEL2", 1, 1); |
Andre Przywara | 06ea44e | 2022-11-17 17:30:43 +0000 | [diff] [blame] | 317 | check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(), |
| 318 | "TRF", 1, 1); |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 319 | |
| 320 | /* v8.5 features */ |
Govindraj Raja | c1be66f | 2024-03-07 14:42:20 -0600 | [diff] [blame] | 321 | check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), "MTE2", |
Govindraj Raja | d7b63ac | 2024-01-26 10:08:37 -0600 | [diff] [blame] | 322 | MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY); |
Andre Przywara | 436b4bb | 2023-02-22 17:55:59 +0000 | [diff] [blame] | 323 | check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1); |
Sona Mathew | d8e89d5 | 2024-04-19 00:24:18 -0500 | [diff] [blame^] | 324 | check_feature(ENABLE_BTI, read_feat_bti_id_field(), "BTI", 1, 1); |
| 325 | check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(), |
| 326 | "RNG_TRAP", 1, 1); |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 327 | |
| 328 | /* v8.6 features */ |
Andre Przywara | 906776e | 2023-03-03 10:30:06 +0000 | [diff] [blame] | 329 | check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(), |
| 330 | "AMUv1p1", 2, 2); |
Andre Przywara | 2f3e79a | 2023-02-01 11:46:31 +0000 | [diff] [blame] | 331 | check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 1); |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 332 | check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV", 1, 2); |
Andre Przywara | 0cf7740 | 2023-01-27 12:25:49 +0000 | [diff] [blame] | 333 | check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(), |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 334 | "TWED", 1, 1); |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 335 | |
Boyan Karatotev | 677ed8a | 2023-02-16 09:45:29 +0000 | [diff] [blame] | 336 | /* |
| 337 | * even though this is a "DISABLE" it does confusingly perform feature |
| 338 | * enablement duties like all other flags here. Check it against the HW |
| 339 | * feature when we intend to diverge from the default behaviour |
| 340 | */ |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 341 | check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), "MTPMU", 1, 1); |
Boyan Karatotev | 677ed8a | 2023-02-16 09:45:29 +0000 | [diff] [blame] | 342 | |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 343 | /* v8.7 features */ |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 344 | check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1); |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 345 | |
Mark Brown | c37eee7 | 2023-03-14 20:13:03 +0000 | [diff] [blame] | 346 | /* v8.9 features */ |
Andre Przywara | 0dda424 | 2023-04-18 16:58:36 +0100 | [diff] [blame] | 347 | check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(), |
Mark Brown | c37eee7 | 2023-03-14 20:13:03 +0000 | [diff] [blame] | 348 | "TCR2", 1, 1); |
Mark Brown | 293a661 | 2023-03-14 20:48:43 +0000 | [diff] [blame] | 349 | check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(), |
| 350 | "S2PIE", 1, 1); |
| 351 | check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(), |
| 352 | "S1PIE", 1, 1); |
| 353 | check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(), |
| 354 | "S2POE", 1, 1); |
| 355 | check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(), |
| 356 | "S1POE", 1, 1); |
Sona Mathew | 3b84c96 | 2023-10-25 16:48:19 -0500 | [diff] [blame] | 357 | check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(), |
| 358 | "CSV2_3", 3, 3); |
Mark Brown | c37eee7 | 2023-03-14 20:13:03 +0000 | [diff] [blame] | 359 | |
Jayanth Dodderi Chidanand | 6931675 | 2022-05-09 12:33:03 +0100 | [diff] [blame] | 360 | /* v9.0 features */ |
Andre Przywara | c97c551 | 2022-11-17 16:42:09 +0000 | [diff] [blame] | 361 | check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(), |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 362 | "BRBE", 1, 2); |
Andre Przywara | 191eff6 | 2022-11-17 16:42:09 +0000 | [diff] [blame] | 363 | check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(), |
| 364 | "TRBE", 1, 1); |
Jayanth Dodderi Chidanand | 6931675 | 2022-05-09 12:33:03 +0100 | [diff] [blame] | 365 | |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 366 | /* v9.2 features */ |
Jayanth Dodderi Chidanand | 605419a | 2023-03-06 23:56:14 +0000 | [diff] [blame] | 367 | check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(), |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 368 | "SME", 1, 2); |
Jayanth Dodderi Chidanand | cfe053a | 2022-11-08 10:31:07 +0000 | [diff] [blame] | 369 | check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(), |
Sona Mathew | 9e505f9 | 2024-03-13 11:33:54 -0500 | [diff] [blame] | 370 | "SME2", 2, 2); |
Mark Brown | 326f295 | 2023-03-14 21:33:04 +0000 | [diff] [blame] | 371 | |
| 372 | /* v9.4 features */ |
| 373 | check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1); |
Sona Mathew | d8e89d5 | 2024-04-19 00:24:18 -0500 | [diff] [blame^] | 374 | check_feature(ENABLE_RME, read_feat_rme_id_field(), "RME", 1, 1); |
Andre Przywara | cc4118d | 2022-11-14 15:42:44 +0000 | [diff] [blame] | 375 | |
| 376 | if (tainted) { |
| 377 | panic(); |
| 378 | } |
Jayanth Dodderi Chidanand | 9461a89 | 2022-01-17 18:57:17 +0000 | [diff] [blame] | 379 | } |