blob: b4d44586d2e51b648e785715a03f8b46d1a1ed7a [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000032#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <gic_v2.h>
34#include <platform.h>
Dan Handley4d2e49d2014-04-11 11:52:12 +010035#include "../drivers/pwrc/fvp_pwrc.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
37 .globl platform_get_entrypoint
38 .globl platform_cold_boot_init
39 .globl plat_secondary_cold_boot_setup
40
41
Achin Gupta4f6ad662013-10-25 09:08:21 +010042 .macro platform_choose_gicmmap param1, param2, x_tmp, w_tmp, res
43 ldr \x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID
44 ldr \w_tmp, [\x_tmp]
45 ubfx \w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH
46 cmp \w_tmp, #BLD_GIC_VE_MMAP
47 csel \res, \param1, \param2, eq
48 .endm
49
50 /* -----------------------------------------------------
51 * void plat_secondary_cold_boot_setup (void);
52 *
53 * This function performs any platform specific actions
54 * needed for a secondary cpu after a cold reset e.g
55 * mark the cpu's presence, mechanism to place it in a
56 * holding pen etc.
57 * TODO: Should we read the PSYS register to make sure
58 * that the request has gone through.
59 * -----------------------------------------------------
60 */
Andrew Thoelke38bde412014-03-18 13:46:55 +000061func plat_secondary_cold_boot_setup
Achin Gupta4f6ad662013-10-25 09:08:21 +010062 /* ---------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +010063 * Power down this cpu.
64 * TODO: Do we need to worry about powering the
65 * cluster down as well here. That will need
66 * locks which we won't have unless an elf-
67 * loader zeroes out the zi section.
68 * ---------------------------------------------
69 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +010070 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +010071 ldr x1, =PWRC_BASE
Dan Handley48a81272014-04-15 12:25:28 +010072 str w0, [x1, #PPOFFR_OFF]
Achin Gupta4f6ad662013-10-25 09:08:21 +010073
74 /* ---------------------------------------------
75 * Deactivate the gic cpu interface as well
76 * ---------------------------------------------
77 */
78 ldr x0, =VE_GICC_BASE
79 ldr x1, =BASE_GICC_BASE
80 platform_choose_gicmmap x0, x1, x2, w2, x1
81 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
82 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
83 str w0, [x1, #GICC_CTLR]
84
85 /* ---------------------------------------------
86 * There is no sane reason to come out of this
87 * wfi so panic if we do. This cpu will be pow-
88 * ered on and reset by the cpu_on pm api
89 * ---------------------------------------------
90 */
91 dsb sy
92 wfi
93cb_panic:
94 b cb_panic
95
96
97 /* -----------------------------------------------------
98 * void platform_get_entrypoint (unsigned int mpid);
99 *
100 * Main job of this routine is to distinguish between
101 * a cold and warm boot.
102 * On a cold boot the secondaries first wait for the
103 * platform to be initialized after which they are
104 * hotplugged in. The primary proceeds to perform the
105 * platform initialization.
106 * On a warm boot, each cpu jumps to the address in its
107 * mailbox.
108 *
109 * TODO: Not a good idea to save lr in a temp reg
110 * TODO: PSYSR is a common register and should be
111 * accessed using locks. Since its not possible
112 * to use locks immediately after a cold reset
113 * we are relying on the fact that after a cold
114 * reset all cpus will read the same WK field
115 * -----------------------------------------------------
116 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000117func platform_get_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +0100118 mov x9, x30 // lr
119 mov x2, x0
120 ldr x1, =PWRC_BASE
121 str w2, [x1, #PSYSR_OFF]
122 ldr w2, [x1, #PSYSR_OFF]
123 ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_MASK
124 cbnz w2, warm_reset
125 mov x0, x2
126 b exit
127warm_reset:
128 /* ---------------------------------------------
129 * A per-cpu mailbox is maintained in the tru-
130 * sted DRAM. Its flushed out of the caches
131 * after every update using normal memory so
132 * its safe to read it here with SO attributes
133 * ---------------------------------------------
134 */
135 ldr x10, =TZDRAM_BASE + MBOX_OFF
136 bl platform_get_core_pos
137 lsl x0, x0, #CACHE_WRITEBACK_SHIFT
138 ldr x0, [x10, x0]
139 cbz x0, _panic
140exit:
141 ret x9
142_panic: b _panic
143
144
145 /* -----------------------------------------------------
146 * void platform_mem_init (void);
147 *
148 * Zero out the mailbox registers in the TZDRAM. The
149 * mmu is turned off right now and only the primary can
150 * ever execute this code. Secondaries will read the
151 * mailboxes using SO accesses. In short, BL31 will
152 * update the mailboxes after mapping the tzdram as
153 * normal memory. It will flush its copy after update.
154 * BL1 will always read the mailboxes with the MMU off
155 * -----------------------------------------------------
156 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000157func platform_mem_init
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158 ldr x0, =TZDRAM_BASE + MBOX_OFF
159 stp xzr, xzr, [x0, #0]
160 stp xzr, xzr, [x0, #0x10]
161 stp xzr, xzr, [x0, #0x20]
162 stp xzr, xzr, [x0, #0x30]
163 ret
164
165
166 /* -----------------------------------------------------
167 * void platform_cold_boot_init (bl1_main function);
168 *
169 * Routine called only by the primary cpu after a cold
170 * boot to perform early platform initialization
171 * -----------------------------------------------------
172 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000173func platform_cold_boot_init
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174 mov x20, x0
175 bl platform_mem_init
Achin Gupta4f6ad662013-10-25 09:08:21 +0100176
177 /* ---------------------------------------------
178 * Give ourselves a small coherent stack to
179 * ease the pain of initializing the MMU and
180 * CCI in assembler
181 * ---------------------------------------------
182 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100183 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100184 bl platform_set_coherent_stack
185
186 /* ---------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100187 * Architectural init. can be generic e.g.
188 * enabling stack alignment and platform spec-
189 * ific e.g. MMU & page table setup as per the
190 * platform memory map. Perform the latter here
191 * and the former in bl1_main.
192 * ---------------------------------------------
193 */
194 bl bl1_early_platform_setup
195 bl bl1_plat_arch_setup
196
197 /* ---------------------------------------------
198 * Give ourselves a stack allocated in Normal
199 * -IS-WBWA memory
200 * ---------------------------------------------
201 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100202 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203 bl platform_set_stack
204
205 /* ---------------------------------------------
206 * Jump to the main function. Returning from it
207 * is a terminal error.
208 * ---------------------------------------------
209 */
210 blr x20
211
212cb_init_panic:
213 b cb_init_panic