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Jiafei Pan46367ad2018-03-02 07:23:30 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diazde97ff32019-01-25 13:28:38 +00007#include <common/bl_common.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <common/debug.h>
9#include <common/interrupt_props.h>
10#include <drivers/arm/gicv2.h>
Antonio Nino Diaz53dec732018-09-25 14:54:23 +010011
Jiafei Pan46367ad2018-03-02 07:23:30 +000012#include "ls_16550.h"
13#include "plat_ls.h"
14#include "soc.h"
15
Antonio Nino Diaz53dec732018-09-25 14:54:23 +010016static const interrupt_prop_t g0_interrupt_props[] = {
17 INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
18 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
Jiafei Pan46367ad2018-03-02 07:23:30 +000019};
20
21gicv2_driver_data_t ls_gic_data = {
22 .gicd_base = GICD_BASE,
23 .gicc_base = GICC_BASE,
Antonio Nino Diaz53dec732018-09-25 14:54:23 +010024 .interrupt_props = g0_interrupt_props,
25 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
Jiafei Pan46367ad2018-03-02 07:23:30 +000026};
27
28/*******************************************************************************
29 * Initialize the UART
30 ******************************************************************************/
31void ls_tsp_early_platform_setup(void)
32{
33 static console_ls_16550_t console;
34 /*
35 * Initialize a different console than already in use to display
36 * messages from TSP
37 */
38 console_ls_16550_register(PLAT_LS1043_UART2_BASE, PLAT_LS1043_UART_CLOCK,
39 PLAT_LS1043_UART_BAUDRATE, &console);
40 NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL32);
41}
42
43/*******************************************************************************
44 * Perform platform specific setup placeholder
45 ******************************************************************************/
46void tsp_platform_setup(void)
47{
48 uint32_t gicc_base, gicd_base;
49
50 /* Initialize the GIC driver, cpu and distributor interfaces */
51 get_gic_offset(&gicc_base, &gicd_base);
52 ls_gic_data.gicd_base = (uintptr_t)gicd_base;
53 ls_gic_data.gicc_base = (uintptr_t)gicc_base;
54 gicv2_driver_init(&ls_gic_data);
55 gicv2_distif_init();
56 gicv2_pcpu_distif_init();
57 gicv2_cpuif_enable();
58}
59
60/*******************************************************************************
61 * Perform the very early platform specific architectural setup here. At the
62 * moment this is only intializes the MMU
63 ******************************************************************************/
64void tsp_plat_arch_setup(void)
65{
66 ls_setup_page_tables(BL32_BASE,
67 (BL32_END - BL32_BASE),
68 BL_CODE_BASE,
69 BL_CODE_END,
70 BL_RO_DATA_BASE,
71 BL_RO_DATA_END
72#if USE_COHERENT_MEM
73 , BL_COHERENT_RAM_BASE,
74 BL_COHERENT_RAM_END
75#endif
76 );
77 enable_mmu_el1(0);
78}