blob: c6073619a72177cfa58aba13cfbed13a693c5fa3 [file] [log] [blame]
Jiafei Pan46367ad2018-03-02 07:23:30 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/debug.h>
8#include <common/interrupt_props.h>
9#include <drivers/arm/gicv2.h>
Antonio Nino Diaz53dec732018-09-25 14:54:23 +010010
Jiafei Pan46367ad2018-03-02 07:23:30 +000011#include "ls_16550.h"
12#include "plat_ls.h"
13#include "soc.h"
14
15#define BL32_END (unsigned long)(&__BL32_END__)
16
Antonio Nino Diaz53dec732018-09-25 14:54:23 +010017static const interrupt_prop_t g0_interrupt_props[] = {
18 INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
19 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
Jiafei Pan46367ad2018-03-02 07:23:30 +000020};
21
22gicv2_driver_data_t ls_gic_data = {
23 .gicd_base = GICD_BASE,
24 .gicc_base = GICC_BASE,
Antonio Nino Diaz53dec732018-09-25 14:54:23 +010025 .interrupt_props = g0_interrupt_props,
26 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
Jiafei Pan46367ad2018-03-02 07:23:30 +000027};
28
29/*******************************************************************************
30 * Initialize the UART
31 ******************************************************************************/
32void ls_tsp_early_platform_setup(void)
33{
34 static console_ls_16550_t console;
35 /*
36 * Initialize a different console than already in use to display
37 * messages from TSP
38 */
39 console_ls_16550_register(PLAT_LS1043_UART2_BASE, PLAT_LS1043_UART_CLOCK,
40 PLAT_LS1043_UART_BAUDRATE, &console);
41 NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL32);
42}
43
44/*******************************************************************************
45 * Perform platform specific setup placeholder
46 ******************************************************************************/
47void tsp_platform_setup(void)
48{
49 uint32_t gicc_base, gicd_base;
50
51 /* Initialize the GIC driver, cpu and distributor interfaces */
52 get_gic_offset(&gicc_base, &gicd_base);
53 ls_gic_data.gicd_base = (uintptr_t)gicd_base;
54 ls_gic_data.gicc_base = (uintptr_t)gicc_base;
55 gicv2_driver_init(&ls_gic_data);
56 gicv2_distif_init();
57 gicv2_pcpu_distif_init();
58 gicv2_cpuif_enable();
59}
60
61/*******************************************************************************
62 * Perform the very early platform specific architectural setup here. At the
63 * moment this is only intializes the MMU
64 ******************************************************************************/
65void tsp_plat_arch_setup(void)
66{
67 ls_setup_page_tables(BL32_BASE,
68 (BL32_END - BL32_BASE),
69 BL_CODE_BASE,
70 BL_CODE_END,
71 BL_RO_DATA_BASE,
72 BL_RO_DATA_END
73#if USE_COHERENT_MEM
74 , BL_COHERENT_RAM_BASE,
75 BL_COHERENT_RAM_END
76#endif
77 );
78 enable_mmu_el1(0);
79}