blob: 80a87487c9dc82bb0c3c1a0cddc14898b72c08f7 [file] [log] [blame]
Varun Wadekarc1d2a282016-11-08 15:46:48 -08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarc1d2a282016-11-08 15:46:48 -08005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef SM_ERR_H
8#define SM_ERR_H
Varun Wadekarc1d2a282016-11-08 15:46:48 -08009
10/* Errors from the secure monitor */
11#define SM_ERR_UNDEFINED_SMC 0xFFFFFFFF /* Unknown SMC (defined by ARM DEN 0028A(0.9.0) */
12#define SM_ERR_INVALID_PARAMETERS -2
13#define SM_ERR_INTERRUPTED -3 /* Got interrupted. Call back with restart SMC */
14#define SM_ERR_UNEXPECTED_RESTART -4 /* Got an restart SMC when we didn't expect it */
15#define SM_ERR_BUSY -5 /* Temporarily busy. Call back with original args */
16#define SM_ERR_INTERLEAVED_SMC -6 /* Got a trusted_service SMC when a restart SMC is required */
17#define SM_ERR_INTERNAL_FAILURE -7 /* Unknown error */
18#define SM_ERR_NOT_SUPPORTED -8
19#define SM_ERR_NOT_ALLOWED -9 /* SMC call not allowed */
20#define SM_ERR_END_OF_INPUT -10
21
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000022#endif /* SM_ERR_H */